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change(soc): rename SOC_CPU_WATCHPOINT_SIZE to SOC_CPU_WATCHPOINT_MAX_REGION_SIZE

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This commit is contained in:
wuzhenghui 2023-11-16 10:26:29 +08:00
parent dd5b091a8b
commit 161bd8bfed
16 changed files with 32 additions and 32 deletions
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2
components/soc/esp32/include/soc/Kconfig.soc_caps.in
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@ -283,7 +283,7 @@ config SOC_CPU_WATCHPOINTS_NUM
int
default 2
config SOC_CPU_WATCHPOINT_SIZE
config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
int
default 64

6
components/soc/esp32/include/soc/soc_caps.h
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@ -155,9 +155,9 @@
#define SOC_CPU_INTR_NUM 32
#define SOC_CPU_HAS_FPU 1
#define SOC_CPU_BREAKPOINTS_NUM 2
#define SOC_CPU_WATCHPOINTS_NUM 2
#define SOC_CPU_WATCHPOINT_SIZE 64 // bytes
#define SOC_CPU_BREAKPOINTS_NUM 2
#define SOC_CPU_WATCHPOINTS_NUM 2
#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 64 // bytes
/*-------------------------- DAC CAPS ----------------------------------------*/
#define SOC_DAC_CHAN_NUM 2

2
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
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@ -223,7 +223,7 @@ config SOC_CPU_WATCHPOINTS_NUM
int
default 2
config SOC_CPU_WATCHPOINT_SIZE
config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
hex
default 0x80000000

6
components/soc/esp32c2/include/soc/soc_caps.h
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@ -101,9 +101,9 @@
#define SOC_CPU_INTR_NUM 32
#define SOC_CPU_HAS_FLEXIBLE_INTC 1
#define SOC_CPU_BREAKPOINTS_NUM 2
#define SOC_CPU_WATCHPOINTS_NUM 2
#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes
#define SOC_CPU_BREAKPOINTS_NUM 2
#define SOC_CPU_WATCHPOINTS_NUM 2
#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes
#define SOC_CPU_IDRAM_SPLIT_USING_PMP 1

2
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
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@ -311,7 +311,7 @@ config SOC_CPU_WATCHPOINTS_NUM
int
default 8
config SOC_CPU_WATCHPOINT_SIZE
config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
hex
default 0x80000000

6
components/soc/esp32c3/include/soc/soc_caps.h
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@ -133,9 +133,9 @@
#define SOC_CPU_INTR_NUM 32
#define SOC_CPU_HAS_FLEXIBLE_INTC 1
#define SOC_CPU_BREAKPOINTS_NUM 8
#define SOC_CPU_WATCHPOINTS_NUM 8
#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes
#define SOC_CPU_BREAKPOINTS_NUM 8
#define SOC_CPU_WATCHPOINTS_NUM 8
#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes
/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
/** The maximum length of a Digital Signature in bits. */

2
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
View File

@ -375,7 +375,7 @@ config SOC_CPU_WATCHPOINTS_NUM
int
default 4
config SOC_CPU_WATCHPOINT_SIZE
config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
hex
default 0x80000000

6
components/soc/esp32c6/include/soc/soc_caps.h
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@ -149,9 +149,9 @@
#define SOC_CPU_HAS_FLEXIBLE_INTC 1
#define SOC_INT_PLIC_SUPPORTED 1 //riscv platform-level interrupt controller
#define SOC_CPU_BREAKPOINTS_NUM 4
#define SOC_CPU_WATCHPOINTS_NUM 4
#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes
#define SOC_CPU_BREAKPOINTS_NUM 4
#define SOC_CPU_WATCHPOINTS_NUM 4
#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes
#define SOC_CPU_HAS_PMA 1
#define SOC_CPU_IDRAM_SPLIT_USING_PMP 1

2
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
View File

@ -359,7 +359,7 @@ config SOC_CPU_WATCHPOINTS_NUM
int
default 4
config SOC_CPU_WATCHPOINT_SIZE
config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
hex
default 0x80000000

6
components/soc/esp32h2/include/soc/soc_caps.h
View File

@ -146,9 +146,9 @@
#define SOC_CPU_HAS_FLEXIBLE_INTC 1
#define SOC_INT_PLIC_SUPPORTED 1 //riscv platform-level interrupt controller
#define SOC_CPU_BREAKPOINTS_NUM 4
#define SOC_CPU_WATCHPOINTS_NUM 4
#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes
#define SOC_CPU_BREAKPOINTS_NUM 4
#define SOC_CPU_WATCHPOINTS_NUM 4
#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes
#define SOC_CPU_HAS_PMA 1
#define SOC_CPU_IDRAM_SPLIT_USING_PMP 1

2
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
View File

@ -311,7 +311,7 @@ config SOC_CPU_WATCHPOINTS_NUM
int
default 4
config SOC_CPU_WATCHPOINT_SIZE
config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
hex
default 0x80000000

6
components/soc/esp32p4/include/soc/soc_caps.h
View File

@ -153,9 +153,9 @@
#define SOC_CPU_HAS_FPU_EXT_ILL_BUG 1 // EXT_ILL CSR doesn't support FLW/FSW
#define SOC_CPU_COPROC_NUM 2
#define SOC_CPU_BREAKPOINTS_NUM 4
#define SOC_CPU_WATCHPOINTS_NUM 4
#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes
#define SOC_CPU_BREAKPOINTS_NUM 4
#define SOC_CPU_WATCHPOINTS_NUM 4
#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes
#define SOC_CPU_HAS_PMA 1
#define SOC_CPU_IDRAM_SPLIT_USING_PMP 1

2
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
View File

@ -323,7 +323,7 @@ config SOC_CPU_WATCHPOINTS_NUM
int
default 2
config SOC_CPU_WATCHPOINT_SIZE
config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
int
default 64

6
components/soc/esp32s2/include/soc/soc_caps.h
View File

@ -142,9 +142,9 @@
#define SOC_CPU_CORES_NUM (1U)
#define SOC_CPU_INTR_NUM 32
#define SOC_CPU_BREAKPOINTS_NUM 2
#define SOC_CPU_WATCHPOINTS_NUM 2
#define SOC_CPU_WATCHPOINT_SIZE 64 // bytes
#define SOC_CPU_BREAKPOINTS_NUM 2
#define SOC_CPU_WATCHPOINTS_NUM 2
#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 64 // bytes
/*-------------------------- DAC CAPS ----------------------------------------*/
#define SOC_DAC_CHAN_NUM 2

2
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
View File

@ -371,7 +371,7 @@ config SOC_CPU_WATCHPOINTS_NUM
int
default 2
config SOC_CPU_WATCHPOINT_SIZE
config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
int
default 64

6
components/soc/esp32s3/include/soc/soc_caps.h
View File

@ -137,9 +137,9 @@
#define SOC_CPU_INTR_NUM 32
#define SOC_CPU_HAS_FPU 1
#define SOC_CPU_BREAKPOINTS_NUM 2
#define SOC_CPU_WATCHPOINTS_NUM 2
#define SOC_CPU_WATCHPOINT_SIZE 64 // bytes
#define SOC_CPU_BREAKPOINTS_NUM 2
#define SOC_CPU_WATCHPOINTS_NUM 2
#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 64 // bytes
/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
/** The maximum length of a Digital Signature in bits. */