mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
feat(esp_hw_support): add api to gpio driver to support output internal clock on GPIO
This commit is contained in:
wuzhenghui
parent
1f10c84a4f
commit
6a436286dc
@ -125,6 +125,10 @@ if(NOT BOOTLOADER_BUILD)
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list(APPEND srcs "sleep_wake_stub.c")
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endif()
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if(CONFIG_SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX OR CONFIG_SOC_GPIO_CLOCKOUT_BY_IO_MUX)
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list(APPEND srcs "esp_clock_output.c")
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endif()
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if(CONFIG_IDF_TARGET_ESP32P4)
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list(REMOVE_ITEM srcs
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"sleep_cpu.c" # TODO: IDF-7528, IDF-7529
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164
components/esp_hw_support/esp_clock_output.c
Normal file
164
components/esp_hw_support/esp_clock_output.c
Normal file
@ -0,0 +1,164 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "driver/gpio.h"
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#include "esp_clock_output.h"
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#include "esp_check.h"
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#include "esp_rom_gpio.h"
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#include "esp_private/clkout_channel.h"
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#include "esp_private/startup_internal.h"
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#include "hal/gpio_hal.h"
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#include "soc/soc_caps.h"
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#include "soc/io_mux_reg.h"
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typedef struct gpio_clock_out_ctx {
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bool is_mapped;
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uint8_t ref_cnt;
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clock_out_channel_t clk_out;
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gpio_num_t mapped_io;
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soc_clkout_sig_id_t mapped_clock;
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} gpio_clock_out_ctx_t;
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static const char *TAG = "gpio_output_clk";
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static portMUX_TYPE s_clkout_channel_lock = portMUX_INITIALIZER_UNLOCKED;
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static gpio_clock_out_ctx_t s_pin_ctrl_clk_out[CLKOUT_CHANNEL_MAX] = {
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[0 ... CLKOUT_CHANNEL_MAX - 1] = {
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.is_mapped = false,
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.ref_cnt = 0,
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}
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};
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static gpio_clock_out_ctx_t* io_mux_pin_ctrl_clk_out_alloc(soc_clkout_sig_id_t clk_sig, gpio_num_t gpio_num)
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{
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gpio_clock_out_ctx_t *allocated_clk_out = NULL;
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#if SOC_GPIO_CLOCKOUT_BY_IO_MUX
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portENTER_CRITICAL(&s_clkout_channel_lock);
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if (!s_pin_ctrl_clk_out[IONUM_TO_CLKOUT(gpio_num)].is_mapped) {
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s_pin_ctrl_clk_out[IONUM_TO_CLKOUT(gpio_num)].is_mapped = true;
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s_pin_ctrl_clk_out[IONUM_TO_CLKOUT(gpio_num)].clk_out = IONUM_TO_CLKOUT(gpio_num);
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allocated_clk_out = &s_pin_ctrl_clk_out[IONUM_TO_CLKOUT(gpio_num)];
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} else if ((s_pin_ctrl_clk_out[IONUM_TO_CLKOUT(gpio_num)].mapped_io == gpio_num) &&
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(s_pin_ctrl_clk_out[IONUM_TO_CLKOUT(gpio_num)].mapped_clock == clk_sig)) {
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allocated_clk_out = &s_pin_ctrl_clk_out[IONUM_TO_CLKOUT(gpio_num)];
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}
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portEXIT_CRITICAL(&s_clkout_channel_lock);
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#elif SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
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for(uint32_t i = 0; i < CLKOUT_CHANNEL_MAX; i++) {
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portENTER_CRITICAL(&s_clkout_channel_lock);
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if (!s_pin_ctrl_clk_out[i].is_mapped) {
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s_pin_ctrl_clk_out[i].is_mapped = true;
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s_pin_ctrl_clk_out[i].clk_out = (clock_out_channel_t)i;
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allocated_clk_out = &s_pin_ctrl_clk_out[i];
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portEXIT_CRITICAL(&s_clkout_channel_lock);
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break;
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} else if ((s_pin_ctrl_clk_out[i].mapped_io == gpio_num) &&
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(s_pin_ctrl_clk_out[i].mapped_clock == clk_sig)) {
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allocated_clk_out = &s_pin_ctrl_clk_out[i];
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portEXIT_CRITICAL(&s_clkout_channel_lock);
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break;
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}
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portEXIT_CRITICAL(&s_clkout_channel_lock);
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}
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#endif
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if (allocated_clk_out != NULL) {
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portENTER_CRITICAL(&s_clkout_channel_lock);
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allocated_clk_out->mapped_io = gpio_num;
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allocated_clk_out->mapped_clock = clk_sig;
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allocated_clk_out->ref_cnt++;
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portEXIT_CRITICAL(&s_clkout_channel_lock);
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}
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return allocated_clk_out;
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}
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static bool io_mux_pin_ctrl_clk_out_sig_try_free(gpio_clock_out_handle_t clk_out_hdl)
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{
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bool do_free = false;
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portENTER_CRITICAL(&s_clkout_channel_lock);
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if (--clk_out_hdl->ref_cnt == 0) {
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do_free = true;
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clk_out_hdl->is_mapped = false;
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}
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portEXIT_CRITICAL(&s_clkout_channel_lock);
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return do_free;
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}
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esp_err_t esp_clock_output_start(soc_clkout_sig_id_t clk_sig, gpio_num_t gpio_num, gpio_clock_out_handle_t *clk_out_hdl)
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{
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ESP_RETURN_ON_FALSE((clk_out_hdl != NULL), ESP_ERR_INVALID_ARG, TAG, "Clock out handle passed in is invalid");
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ESP_RETURN_ON_FALSE(IS_VALID_CLKOUT_IO(gpio_num), ESP_ERR_INVALID_ARG, TAG, "%s", "Output GPIO number error");
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gpio_clock_out_ctx_t* new_hdl= io_mux_pin_ctrl_clk_out_alloc(clk_sig, gpio_num);
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#if SOC_GPIO_CLOCKOUT_BY_IO_MUX
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ESP_RETURN_ON_FALSE((new_hdl != NULL), ESP_ERR_INVALID_ARG, TAG, "Selected clock out IO is already mapped to other internal clock source");
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#elif SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
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ESP_RETURN_ON_FALSE((new_hdl != NULL), ESP_FAIL, TAG, "Maximum support for %d output clock signals, no available clock_out channel for assignment", CLKOUT_CHANNEL_MAX);
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#endif
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if (new_hdl->ref_cnt == 1) {
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uint32_t clk_out_mask = (new_hdl->clk_out == CLKOUT_CHANNEL_1) ? CLK_OUT1 :
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(new_hdl->clk_out == CLKOUT_CHANNEL_2) ? CLK_OUT2 :
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(new_hdl->clk_out == CLKOUT_CHANNEL_3) ? CLK_OUT3 : 0;
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uint32_t clk_out_shift = (new_hdl->clk_out == CLKOUT_CHANNEL_1) ? CLK_OUT1_S :
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(new_hdl->clk_out == CLKOUT_CHANNEL_2) ? CLK_OUT2_S :
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(new_hdl->clk_out == CLKOUT_CHANNEL_3) ? CLK_OUT3_S : 0;
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portENTER_CRITICAL(&s_clkout_channel_lock);
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gpio_ll_set_pin_ctrl(clk_sig, clk_out_mask, clk_out_shift);
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portEXIT_CRITICAL(&s_clkout_channel_lock);
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#if SOC_GPIO_CLOCKOUT_BY_IO_MUX
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uint32_t clk_out_func = (new_hdl->clk_out == CLKOUT_CHANNEL_1) ? FUNC_CLK_OUT1 :
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(new_hdl->clk_out == CLKOUT_CHANNEL_2) ? FUNC_CLK_OUT2 :
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(new_hdl->clk_out == CLKOUT_CHANNEL_3) ? FUNC_CLK_OUT3 : 0;
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], clk_out_func);
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#elif SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
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uint32_t gpio_clk_out_sig_idx = (new_hdl->clk_out == CLKOUT_CHANNEL_1) ? CLK_OUT_OUT1_IDX :
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(new_hdl->clk_out == CLKOUT_CHANNEL_2) ? CLK_OUT_OUT2_IDX :
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(new_hdl->clk_out == CLKOUT_CHANNEL_3) ? CLK_OUT_OUT3_IDX : SIG_GPIO_OUT_IDX;
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gpio_set_pull_mode(gpio_num, GPIO_FLOATING);
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
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gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
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esp_rom_gpio_connect_out_signal(gpio_num, gpio_clk_out_sig_idx, false, false);
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#endif
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}
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*clk_out_hdl = new_hdl;
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return ESP_OK;
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}
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esp_err_t esp_clock_output_stop(gpio_clock_out_handle_t clk_out_hdl)
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{
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assert(clk_out_hdl != NULL);
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ESP_RETURN_ON_FALSE(clk_out_hdl->is_mapped, ESP_ERR_INVALID_STATE, TAG, "%s", "Clock outputting is already disabled");
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if (io_mux_pin_ctrl_clk_out_sig_try_free(clk_out_hdl)) {
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[clk_out_hdl->mapped_io], PIN_FUNC_GPIO);
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esp_rom_gpio_connect_out_signal(clk_out_hdl->mapped_io, SIG_GPIO_OUT_IDX, false, false);
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gpio_set_direction(clk_out_hdl->mapped_io, GPIO_MODE_DISABLE);
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}
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return ESP_OK;
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}
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#if CONFIG_IDF_TARGET_ESP32
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// Due to a hardware bug, PIN_CTRL cannot select 0xf output, whereas 0xf is the default value.
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__attribute__((constructor))
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static void esp_clock_output_pin_ctrl_init(void)
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{
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gpio_ll_set_pin_ctrl(0, CLK_OUT1, CLK_OUT1_S);
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gpio_ll_set_pin_ctrl(0, CLK_OUT2, CLK_OUT2_S);
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gpio_ll_set_pin_ctrl(0, CLK_OUT3, CLK_OUT3_S);
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}
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#endif
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53
components/esp_hw_support/include/esp_clock_output.h
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53
components/esp_hw_support/include/esp_clock_output.h
Normal file
@ -0,0 +1,53 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdbool.h>
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#include <stdint.h>
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#include "sdkconfig.h"
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#include "soc/soc_caps.h"
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#include "soc/clk_tree_defs.h"
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#include "esp_err.h"
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#include "driver/gpio.h"
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#include "freertos/FreeRTOS.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX || SOC_GPIO_CLOCKOUT_BY_IO_MUX
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typedef struct gpio_clock_out_ctx* gpio_clock_out_handle_t;
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/**
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* @brief Start output specified clock signal to specified GPIO, will also
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* initialize the clk_out_hdl.
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*
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* @param[in] clk_src The clock signal source to be mapped to GPIOs
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* @param[in] gpio_num GPIO number to be mapped soc_root_clk signal source
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* @param[out] clk_out_hdl Clock output controll handler
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* @return
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* - ESP_OK: Output specified clock signal to specified GPIO successfully
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* - ESP_ERR_INVALID_ARG: Specified GPIO not supported to output internal clock
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* or specified GPIO is already mapped to other internal clock source.
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* - ESP_FAIL: There are no clock out signals that can be allocated.
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*/
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esp_err_t esp_clock_output_start(soc_clkout_sig_id_t clk_sig, gpio_num_t gpio_num, gpio_clock_out_handle_t *clk_out_hdl);
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/**
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* @brief Stop clock signal to GPIO outputting
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* @param[in] clk_out_hdl Clock output controll handle
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* @return
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* - ESP_OK: Disable the clock output on GPIO successfully
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* - ESP_ERR_INVALID_STATE The clock in handle is already in the disabled state
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*/
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esp_err_t esp_clock_output_stop(gpio_clock_out_handle_t clk_out_hdl);
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#endif
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#ifdef __cplusplus
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}
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#endif
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@ -0,0 +1,48 @@
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/*
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* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "sdkconfig.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum clock_out_channel {
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CLKOUT_CHANNEL_1,
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CLKOUT_CHANNEL_2,
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CLKOUT_CHANNEL_3,
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CLKOUT_CHANNEL_MAX,
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} clock_out_channel_t;
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#if SOC_GPIO_CLOCKOUT_BY_IO_MUX
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#if CONFIG_IDF_TARGET_ESP32
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#define CLKOUT_CHANNEL1_GPIO GPIO_NUM_0
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#define CLKOUT_CHANNEL2_GPIO GPIO_NUM_3
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#define CLKOUT_CHANNEL3_GPIO GPIO_NUM_1
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#define FUNC_CLK_OUT1 FUNC_GPIO0_CLK_OUT1
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#define FUNC_CLK_OUT2 FUNC_U0RXD_CLK_OUT2
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#define FUNC_CLK_OUT3 FUNC_U0TXD_CLK_OUT3
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#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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#define CLKOUT_CHANNEL1_GPIO GPIO_NUM_20
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#define CLKOUT_CHANNEL2_GPIO GPIO_NUM_19
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#define CLKOUT_CHANNEL3_GPIO GPIO_NUM_18
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#define FUNC_CLK_OUT1 FUNC_GPIO20_CLK_OUT1
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#define FUNC_CLK_OUT2 FUNC_GPIO19_CLK_OUT2
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#define FUNC_CLK_OUT3 FUNC_DAC_2_CLK_OUT3
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#endif
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#define IS_VALID_CLKOUT_IO(gpio_num) ((gpio_num == CLKOUT_CHANNEL1_GPIO) || (gpio_num == CLKOUT_CHANNEL2_GPIO) || (gpio_num == CLKOUT_CHANNEL3_GPIO))
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#elif SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
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#define IS_VALID_CLKOUT_IO(gpio_num) GPIO_IS_VALID_GPIO(gpio_num)
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#endif
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#define IONUM_TO_CLKOUT(gpio_num) ((gpio_num == CLKOUT_CHANNEL1_GPIO) ? CLKOUT_CHANNEL_1 : \
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(gpio_num == CLKOUT_CHANNEL2_GPIO) ? CLKOUT_CHANNEL_2 : \
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(gpio_num == CLKOUT_CHANNEL3_GPIO) ? CLKOUT_CHANNEL_3 : 0)
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#ifdef __cplusplus
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}
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#endif
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@ -315,6 +315,10 @@ config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
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hex
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default 0xEF0FEA
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config SOC_GPIO_CLOCKOUT_BY_IO_MUX
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bool
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default y
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config SOC_I2C_NUM
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int
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default 2
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@ -441,6 +441,21 @@ typedef enum {
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SDMMC_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_160M as the source clock */
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} soc_periph_sdmmc_clk_src_t;
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//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
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typedef enum {
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CLKOUT_SIG_I2S0 = 0, /*!< I2S0 clock, depends on the i2s driver configuration */
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CLKOUT_SIG_PLL = 1, /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */
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CLKOUT_SIG_RC_SLOW = 4, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
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CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */
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CLKOUT_SIG_APLL = 6, /*!< Divided by PLL, frequency is configurable */
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CLKOUT_SIG_REF_TICK = 12, /*!< Divided by APB clock, usually be 1MHz */
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CLKOUT_SIG_PLL_F80M = 13, /*!< From PLL, usually be 80MHz */
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CLKOUT_SIG_RC_FAST = 14, /*!< RC fast clock, about 8MHz */
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CLKOUT_SIG_I2S1 = 15, /*!< I2S1 clock, depends on the i2s driver configuration */
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CLKOUT_SIG_INVALID = 0xFF,
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} soc_clkout_sig_id_t;
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#ifdef __cplusplus
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}
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#endif
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@ -1,20 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC_CLKOUT_CHANNEL_H
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#define _SOC_CLKOUT_CHANNEL_H
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//CLKOUT channels
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#define CLKOUT_IOMUX_FUNC_NUM 1
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#define CLKOUT_GPIO0_DIRECT_CHANNEL CLKOUT_CHANNEL_1
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#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM 0
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#define CLKOUT_GPIO3_DIRECT_CHANNEL CLKOUT_CHANNEL_2
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#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM 3
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#define CLKOUT_GPIO1_DIRECT_CHANNEL CLKOUT_CHANNEL_3
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#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM 1
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#endif
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@ -181,6 +181,9 @@
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// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM: 1, 3, 5, 6, 7, 8, 9, 10, 11, 16, 17, 18, 19, 21, 22, 23)
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#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0xEF0FEAULL
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// The Clock Out singnal is binding to the pin's IO_MUX function
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#define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1)
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/*-------------------------- I2C CAPS ----------------------------------------*/
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// ESP32 has 2 I2C
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#define SOC_I2C_NUM (2)
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@ -279,6 +279,10 @@ config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
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hex
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default 0x00000000001FFFC0
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config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
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bool
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default y
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config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
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int
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default 8
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@ -285,6 +285,16 @@ typedef enum {
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LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
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} soc_periph_ledc_clk_src_legacy_t;
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//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
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typedef enum {
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CLKOUT_SIG_PLL = 1, /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */
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CLKOUT_SIG_RC_SLOW = 4, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
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CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */
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CLKOUT_SIG_PLL_F80M = 13, /*!< From PLL, usually be 80MHz */
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CLKOUT_SIG_RC_FAST = 14, /*!< RC fast clock, about 8MHz */
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CLKOUT_SIG_INVALID = 0xFF,
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} soc_clkout_sig_id_t;
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#ifdef __cplusplus
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}
|
||||
#endif
|
||||
|
||||
@ -1,12 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _SOC_CLKOUT_CHANNEL_H
|
||||
#define _SOC_CLKOUT_CHANNEL_H
|
||||
|
||||
// ESP32C2 CLKOUT signals has no corresponding iomux pins
|
||||
|
||||
#endif
|
||||
@ -136,6 +136,9 @@
|
||||
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_20)
|
||||
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000001FFFC0ULL
|
||||
|
||||
// The Clock Out singnal is route to the pin by GPIO matrix
|
||||
#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
|
||||
|
||||
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
|
||||
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
|
||||
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
|
||||
|
||||
@ -371,6 +371,10 @@ config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
|
||||
hex
|
||||
default 0x00000000003FFFC0
|
||||
|
||||
config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
|
||||
int
|
||||
default 8
|
||||
|
||||
@ -357,6 +357,16 @@ typedef enum {
|
||||
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
|
||||
} soc_periph_ledc_clk_src_legacy_t;
|
||||
|
||||
//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
CLKOUT_SIG_PLL = 1, /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */
|
||||
CLKOUT_SIG_RC_SLOW = 4, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
|
||||
CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */
|
||||
CLKOUT_SIG_PLL_F80M = 13, /*!< From PLL, usually be 80MHz */
|
||||
CLKOUT_SIG_RC_FAST = 14, /*!< RC fast clock, about 17.5MHz */
|
||||
CLKOUT_SIG_INVALID = 0xFF,
|
||||
} soc_clkout_sig_id_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1,12 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _SOC_CLKOUT_CHANNEL_H
|
||||
#define _SOC_CLKOUT_CHANNEL_H
|
||||
|
||||
// ESP32C3 CLKOUT signals has no corresponding iomux pins
|
||||
|
||||
#endif
|
||||
@ -174,6 +174,9 @@
|
||||
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_21)
|
||||
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000003FFFC0ULL
|
||||
|
||||
// The Clock Out singnal is route to the pin by GPIO matrix
|
||||
#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
|
||||
|
||||
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
|
||||
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
|
||||
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
|
||||
|
||||
@ -475,6 +475,10 @@ config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RTCIO_PIN_COUNT
|
||||
int
|
||||
default 8
|
||||
|
||||
@ -463,6 +463,22 @@ typedef enum {
|
||||
PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the default clock choice */
|
||||
} soc_periph_parlio_clk_src_t;
|
||||
|
||||
//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
CLKOUT_SIG_PLL = 1, /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */
|
||||
CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */
|
||||
CLKOUT_SIG_PLL_F80M = 13, /*!< From PLL, usually be 80MHz */
|
||||
CLKOUT_SIG_CPU = 16, /*!< CPU clock */
|
||||
CLKOUT_SIG_AHB = 17, /*!< AHB clock */
|
||||
CLKOUT_SIG_APB = 18, /*!< APB clock */
|
||||
CLKOUT_SIG_XTAL32K = 21, /*!< External 32kHz crystal clock */
|
||||
CLKOUT_SIG_EXT32K = 22, /*!< External slow clock input through XTAL_32K_P */
|
||||
CLKOUT_SIG_RC_FAST = 23, /*!< RC fast clock, about 17.5MHz */
|
||||
CLKOUT_SIG_RC_32K = 24, /*!< Internal slow RC oscillator */
|
||||
CLKOUT_SIG_RC_SLOW = 25, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
|
||||
CLKOUT_SIG_INVALID = 0xFF,
|
||||
} soc_clkout_sig_id_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1,8 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
// ESP32C6 CLKOUT signals has no corresponding iomux pins
|
||||
@ -208,6 +208,9 @@
|
||||
// Support to hold a single digital I/O when the digital domain is powered off
|
||||
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
|
||||
|
||||
// The Clock Out singnal is route to the pin by GPIO matrix
|
||||
#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
|
||||
|
||||
/*-------------------------- RTCIO CAPS --------------------------------------*/
|
||||
#define SOC_RTCIO_PIN_COUNT 8
|
||||
#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /* This macro indicates that the target has separate RTC IOMUX hardware feature,
|
||||
|
||||
@ -467,6 +467,10 @@ config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RTCIO_PIN_COUNT
|
||||
int
|
||||
default 8
|
||||
|
||||
@ -479,6 +479,20 @@ typedef enum {
|
||||
MSPI_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */
|
||||
} soc_periph_mspi_clk_src_t;
|
||||
|
||||
//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */
|
||||
CLKOUT_SIG_CPU = 16, /*!< CPU clock */
|
||||
CLKOUT_SIG_AHB = 17, /*!< AHB clock */
|
||||
CLKOUT_SIG_APB = 18, /*!< APB clock */
|
||||
CLKOUT_SIG_XTAL32K = 21, /*!< External 32kHz crystal clock */
|
||||
CLKOUT_SIG_EXT32K = 22, /*!< External slow clock input through XTAL_32K_P */
|
||||
CLKOUT_SIG_RC_FAST = 23, /*!< RC fast clock, about 17.5MHz */
|
||||
CLKOUT_SIG_RC_32K = 24, /*!< Internal slow RC oscillator */
|
||||
CLKOUT_SIG_RC_SLOW = 25, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
|
||||
CLKOUT_SIG_INVALID = 0xFF,
|
||||
} soc_clkout_sig_id_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1,8 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
// ESP32H2 CLKOUT signals has no corresponding iomux pins
|
||||
@ -210,6 +210,9 @@
|
||||
// Support to hold a single digital I/O when the digital domain is powered off
|
||||
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
|
||||
|
||||
// The Clock Out singnal is route to the pin by GPIO matrix
|
||||
#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
|
||||
|
||||
/*-------------------------- RTCIO CAPS --------------------------------------*/
|
||||
/* No dedicated LP_IOMUX subsystem on ESP32-H2. LP functions are still supported
|
||||
* for hold, wake & 32kHz crystal functions - via LP_AON registers */
|
||||
|
||||
@ -1,8 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
// ESP32P4 CLKOUT signals has no corresponding iomux pins
|
||||
@ -367,6 +367,10 @@ config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
|
||||
hex
|
||||
default 0x00007FFFFC000000
|
||||
|
||||
config SOC_GPIO_CLOCKOUT_BY_IO_MUX
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
|
||||
int
|
||||
default 8
|
||||
|
||||
@ -415,6 +415,18 @@ typedef enum {
|
||||
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
|
||||
} soc_periph_ledc_clk_src_legacy_t;
|
||||
|
||||
//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
CLKOUT_SIG_PLL = 1, /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */
|
||||
CLKOUT_SIG_RC_SLOW = 4, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
|
||||
CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */
|
||||
CLKOUT_SIG_APLL = 6, /*!< Divided by PLL, frequency is configurable */
|
||||
CLKOUT_SIG_REF_TICK = 12, /*!< Divided by APB clock, usually be 1MHz */
|
||||
CLKOUT_SIG_PLL_F80M = 13, /*!< From PLL, usually be 80MHz */
|
||||
CLKOUT_SIG_RC_FAST = 14, /*!< RC fast clock, about 17.5MHz */
|
||||
CLKOUT_SIG_INVALID = 0xFF,
|
||||
} soc_clkout_sig_id_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1,20 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _SOC_CLKOUT_CHANNEL_H
|
||||
#define _SOC_CLKOUT_CHANNEL_H
|
||||
|
||||
//CLKOUT channels
|
||||
#define CLKOUT_IOMUX_FUNC_NUM 3
|
||||
|
||||
#define CLKOUT_GPIO20_DIRECT_CHANNEL CLKOUT_CHANNEL_1
|
||||
#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM 20
|
||||
#define CLKOUT_GPIO19_DIRECT_CHANNEL CLKOUT_CHANNEL_2
|
||||
#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM 19
|
||||
#define CLKOUT_GPIO18_DIRECT_CHANNEL CLKOUT_CHANNEL_3
|
||||
#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM 18
|
||||
|
||||
#endif
|
||||
@ -171,6 +171,9 @@
|
||||
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_26~GPIO_NUM_46)
|
||||
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00007FFFFC000000ULL
|
||||
|
||||
// The Clock Out singnal is binding to the pin's IO_MUX function
|
||||
#define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1)
|
||||
|
||||
/*-------------------------- Dedicated GPIO CAPS ---------------------------------------*/
|
||||
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
|
||||
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
|
||||
|
||||
@ -435,6 +435,10 @@ config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
|
||||
hex
|
||||
default 0x0001FFFFFC000000
|
||||
|
||||
config SOC_GPIO_CLOCKOUT_BY_IO_MUX
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
|
||||
int
|
||||
default 8
|
||||
|
||||
@ -444,6 +444,15 @@ typedef enum {
|
||||
SDMMC_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
} soc_periph_sdmmc_clk_src_t;
|
||||
|
||||
//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
CLKOUT_SIG_PLL = 1, /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */
|
||||
CLKOUT_SIG_RC_SLOW = 4, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
|
||||
CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */
|
||||
CLKOUT_SIG_PLL_F80M = 13, /*!< From PLL, usually be 80MHz */
|
||||
CLKOUT_SIG_RC_FAST = 14, /*!< RC fast clock, about 17.5MHz */
|
||||
CLKOUT_SIG_INVALID = 0xFF,
|
||||
} soc_clkout_sig_id_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@ -1,20 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
//CLKOUT channels
|
||||
#define CLKOUT_IOMUX_FUNC_NUM 3
|
||||
|
||||
#define CLKOUT_GPIO20_DIRECT_CHANNEL CLKOUT_CHANNEL_1
|
||||
#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM 20
|
||||
#define CLKOUT_GPIO19_DIRECT_CHANNEL CLKOUT_CHANNEL_2
|
||||
#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM 19
|
||||
#define CLKOUT_GPIO18_DIRECT_CHANNEL CLKOUT_CHANNEL_3
|
||||
#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM 18
|
||||
|
||||
// ESP32S3 has two other sets of GPIO pins which could route to CLKOUT_CHANNEL_1/2/3 through IO_MUX
|
||||
// Please check TRM IO MUX Function List table if needed
|
||||
@ -177,6 +177,9 @@
|
||||
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_26~GPIO_NUM_48)
|
||||
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0001FFFFFC000000ULL
|
||||
|
||||
// The Clock Out singnal is binding to the pin's IO_MUX function
|
||||
#define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1)
|
||||
|
||||
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
|
||||
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
|
||||
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user