alex/esp-idf
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41 Commits

Author SHA1 Message Date
Omar Chebib
752026a174 Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master' 
G0: RISC-V targets have now an independent G0 layer

See merge request espressif/esp-idf!17926
 2022-06-16 11:53:39 +08:00
Omar Chebib
5bcd9b2db8 G0: RISC-V targets have now an independent G0 layer 
G0 doesn't depend on any G1+ layer for RISC-V based targets
 2022-06-14 15:00:53 +08:00
Darian Leung
61eb7baa6b esp_hw_support: Add esp_cpu.h abstraction and API 
This commit updates the esp_cpu.h API. The new API presents a new
abstraction of the CPU where CPU presents the following interfaces:

- CPU Control (to stall/unstall/reset the CPU)
- CPU Registers (to read registers commonly used in SW such as SP, PC)
- CPU Interrupts (to inquire/allocate/control the CPUs 32 interrupts)
- Memory Port (to configure the CPU's memory bus for memory protection)
- Debugging (to configure/control the CPU's debugging port)

Note: Also added FORCE_INLINE_ATTR to the DoxyFile in order to pass doc
        builds for esp_cpu.h
 2022-06-14 14:30:58 +08:00
Marius Vikhammer
cf1b222cac build system: removed target component 
After refactoring the target components (e.g. esp32) no longer contained any real functionality.
What remained in these components have been moved elsewhere and the component itself deleted from the
build system.
 2022-05-24 09:12:59 +08:00
Marius Vikhammer
9362434c47 build-system: add property for architecture (riscv/xtensa) 
riscv/xtensa is now a common component.
 2022-05-20 09:00:32 +08:00
Erhan Kurubas
0fc0254734 semihosting: version 2 2022-05-05 09:12:42 +00:00
Alexey Gerenkov
dea45a9d72 riscv: Use semihosting to set breakpoint and watchpoint when running under debugger 2022-02-24 08:55:40 +00:00
Alexey Gerenkov
72822dfc8f riscv: Adds support for returning from exception handler 2022-02-24 08:55:40 +00:00
Alexey Gerenkov
54569fb001 riscv: Fixes GDB backtrace of interrupted threads 
Save missed SP value on stack
 2022-02-24 08:55:40 +00:00
Ivan Grokhotkov
336d0b64de riscv: fix panic_reasons being an instance of enum, not type name 2022-01-27 11:00:09 +07:00
laokaiyao
cf049e15ed esp8684: rename target to esp32c2 2022-01-19 11:08:57 +08:00
Ivan Grokhotkov
876f4d6a1c vfs: add support for semihosting on ESP32-C3 2022-01-14 17:29:03 +01:00
Omar Chebib
220e52fca1 RISC-V: Fix vectors.S assembly file indentation and macro usage 
The file is now more consistent as the macros have been fixed, more comments
have been added and the indentation is now using spaces only.
 2021-11-15 17:17:24 +08:00
Cao Sen Miao
36f6d16b8d ESP8684: add soc, riscv, newlib support 2021-11-06 17:33:44 +08:00
Omar Chebib
0f6f3c0ece RISC-V: fix usage of special register when interrupts are enabled 2021-10-25 16:31:34 +08:00
Shu Chen
75bd02bd46 esp32h2: add some more fixes and TODOs 2021-07-01 20:36:39 +08:00
Shu Chen
ee23a489b9 esp32h2: code clean up 2021-07-01 19:53:50 +08:00
Shu Chen
2b9e8fed71 esp32h2: add esp32h2 build target 
Add esp32h2 support in the following components:
 * Kconfig
 * components/esptool_py
 * components/riscv
 * components/xtensa
 * tools
 2021-07-01 19:51:33 +08:00
Renz Bagaporo
d920aa52be xtensa: simplify build script 2021-02-26 19:45:48 +08:00
Renz Bagaporo
b1027005df arch: move stdatomic 2021-02-26 18:40:00 +08:00
Renz Bagaporo
7e0e91bf76 arch: move debug helpers 2021-02-26 13:34:29 +08:00
Renz Bagaporo
6f7072fc03 arch: move esp_attr.h to esp_common 2021-02-26 13:34:29 +08:00
Renz Bagaporo
91a5770fd2 arch: move shared stack implementation to esp_system 2021-02-26 13:34:29 +08:00
Marius Vikhammer
c36dd7834f core: fix cases where riscv SP were not 16 byte aligned 
RISC-V stack pointer should always be 16 byte aligned, but for some cases where
we were doing manual SP manipulation this was not always the case.
 2021-02-19 11:26:21 +08:00
Marius Vikhammer
eec2419390 system: enable shared stack watchpoint 
Enable shared stack watchpoint for overflow detection

Enable unit tests:
 * "test printf using shared buffer stack" for C3
 * "Test vTaskDelayUntil" for S2
 * "UART can do poll()" for C3
 2021-02-18 15:38:30 +08:00
Martin Vychodil
69096ddce5 Security: ESP32C3 memory protection feature (IRAM0/DRAM0) 
Software support for PMS module.
Allows controlled memory access to IRAM (R/W/X) and DRAM0 (R/W)
On/locked by default, configurable in Kconfig (esp_system)

Closes https://jira.espressif.com:8443/browse/IDF-2092
 2021-01-27 08:44:03 +01:00
Li Shuai
355dd10257 light sleep: dfs support for esp32c3 2021-01-19 14:50:58 +08:00
Jakob Hasse
b51889dccb system: stack watchpoint support on C3 
Closes IDF-2307
 2021-01-14 17:46:44 +08:00
morris
7a71cedf87 interrupt: filter out reserved int number by decoding risc-v JAL instruction 2021-01-05 15:39:46 +08:00
morris
9e7d2c0065 esp32c3: format and clean up interrupt and os port code 2021-01-05 15:39:46 +08:00
Felipe Neves
72e4655d4e interrupt: removed descriptor table from esp32c3 interrupt hal. 2021-01-05 15:39:46 +08:00
Felipe Neves
544a3f7df5 interrupt-allocator: reject vector allocation if its marked as not-implemented. and search to next available 2021-01-05 15:39:46 +08:00
Felipe Neves
ec5acf91ee esp_shared_stack: enable shared stack function for riscv and reenable the unit test 2021-01-05 15:39:46 +08:00
Felipe Neves
f4781d3b1d freertos: riscv port now uses interrupt allocator and crosscore interrupt 2021-01-05 15:39:46 +08:00
Felipe Neves
810be86f21 freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port. 
The riscv vectors.S in riscv component contains the trap vector, which is responsible to
defer interrupts and examine if a task context switch is needed, this change cleans up
this code by hiding all freertos details behind on two functions rtos_it_enter/exit and
their implementations are placed in freertos riscv port files.
 2021-01-05 15:39:46 +08:00
Omar Chebib
c218f669ba panic on RISC-V: Take into account Merge Request comments 2020-12-31 15:46:17 +08:00
Omar Chebib
a90dcfba1a panic: Add support for SoC-level panic 
Activate "invalid access to cache raises panic (PRO CPU)" CI unit
test in order to test SoC-level panics.
 2020-12-31 15:46:17 +08:00
Omar Chebib
b6a450f824 panic: Add support for SoC-level panic 
SoC level exceptions such as watchdog timer and cache errors are now supported.
Such exceptions now triggers a panic, giving more information about how
and when it happened.
 2020-12-31 15:46:17 +08:00
Angus Gratton
e2d4f0e320 riscv: Place stdatomic file in iram 2020-12-24 14:18:01 +11:00
Renz Bagaporo
4cc6b5571b esp_system: support riscv panic 2020-11-13 07:49:11 +11:00
Angus Gratton
fccab8f4ef riscv: Add new arch-level component 
Changes come from internal branch commit a6723fc
 2020-11-12 09:33:18 +11:00