morris
c4e84751a5
driver: fix public header exceptions for driver
2022-07-22 00:12:36 +00:00
morris
741b031e83
soc: added SOC_TOUCH_SENSE_SUPPORTED macro
2022-07-22 00:12:36 +00:00
laokaiyao
edee3ee3cd
i2s: add slot sequence table
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Closes: https://github.com/espressif/esp-idf/issues/9208
When I2S is configured into different modes, the slot sequence varies.
This commit updates slot sequence tables and corresponding descriptions
in (both code and programming guide).
2022-07-21 15:52:39 +08:00
laokaiyao
90866e99fb
i2s: add basic examples for STD/TDM/PDM mode
2022-07-21 15:52:39 +08:00
morris
4154eaec93
sdm: clean up soc/hal/ll code
2022-07-20 14:59:50 +08:00
Armando (Dou Yiwen)
9f6f61345b
Merge branch 'feature/adc_driver_ng' into 'master'
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ADC Driver NG
Closes IDF-4560, IDF-3908, IDF-4225, IDF-2482, IDF-4111, IDF-3610, IDF-4058, IDF-3801, IDF-3636, IDF-2537, IDF-4310, IDF-5150, IDF-5151, and IDF-4979
See merge request espressif/esp-idf!17960
2022-07-19 21:28:31 +08:00
Cao Sen Miao
53580a62b5
I2C: Fullfill the I2C clock tree, and support 26M XTAL on ESP32-C2
2022-07-19 11:41:42 +08:00
Armando
5b523a3313
esp_adc: new esp_adc component and adc drivers
2022-07-15 18:31:00 +08:00
Jiang Jiang Jian
3630713e5f
Merge branch 'docs/esp32c2_sys_feature_api_guides' into 'master'
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docs: update system API-guides for ESP32-C2
Closes IDF-4202, IDF-4213, and IDF-4222
See merge request espressif/esp-idf!18979
2022-07-12 10:59:12 +08:00
Marius Vikhammer
d62421619c
docs: update system API-guides for ESP32-C2
2022-07-12 09:32:43 +08:00
Song Ruo Jing
ea97cc93ea
Merge branch 'feature/c2_systimer_26mhz' into 'master'
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esp32c2: 26 MHz XTAL support: Kconfig option, systimer support
Closes IDF-5412 and IDF-5413
See merge request espressif/esp-idf!18835
2022-07-11 16:17:25 +08:00
songruojing
b3d8db3ae2
bootloader, esp_system: esp32c2 console uart to support 26MHz xtal
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Gets the XTAL frequency from the RTC storage register, remove UART_CLK_FREQ_ROM macro from soc.h
2022-07-11 12:24:58 +08:00
Ivan Grokhotkov
5b54ae76d4
esp_timer, hal: add support for non-integer systimer frequency
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When ESP32-C2 is paired with a 26 MHz XTAL, the systimer tick
frequency becomes equal to 26 / 2.5 = 10.4 MHz. Previously we always
assumed that systimer tick frequency is integer (and 1 MHz * power of
two, above that!).
This commit introduces a new LL macro, SYSTIMER_LL_TICKS_PER_US_DIV.
It should be set in such a way that:
1. SYSTIMER_LL_TICKS_PER_US / SYSTIMER_LL_TICKS_PER_US_DIV equals the
actual systimer tick frequency,
2. and SYSTIMER_LL_TICKS_PER_US is integer.
For ESP32-C2 this means that SYSTIMER_LL_TICKS_PER_US = 52 and
SYSTIMER_LL_TICKS_PER_US_DIV = 5.
This introduced two possible issues:
1. Overflow when multiplying systimer counter by 5
- Should not be an issue, since systimer counter is 52-bit, so
counter * 5 is no more than 55-bit.
2. The code needs to perform:
- divide by 5: when converting from microseconds to ticks
- divide by 52: when converting from ticks to microseconds
The latter potentially introduces a performance issue for the
esp_timer_get_time function.
2022-07-11 12:24:37 +08:00
Jiang Jiang Jian
a7bf3af687
Merge branch 'bugfix/reset_ble_hw_on_inititalization' into 'master'
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component/bt: reset Bluetooth hardware during controller inititalization on ESP32-C3/ESP32-S3
Closes BT-2402
See merge request espressif/esp-idf!18831
2022-07-08 16:21:41 +08:00
Michael (XIAO Xufeng)
a58362a429
Merge branch 'feature/efuse_rev_major_minor' into 'master'
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efuse: Adds major and minor versions
See merge request espressif/esp-idf!18255
2022-07-07 11:48:54 +08:00
wangmengyang
f86efb2bc2
fix licence copyright for header file syscon_reg.h on ESP32C3 and ESP32S3
2022-07-06 16:24:03 +08:00
wangmengyang
1d55f12c2d
component/bt: reset Bluetooth hardware during controller inititalization on ESP32-C3/ESP32-S3
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1. Rename MACROs SYSTEM_WIFI_RST_EN register bit fields to be more recognizable
2. reset Bluetooth baseband and clock bits to fix the issue of task watchdog triggered during controller initialization due to invalid hardware state
2022-07-06 16:23:48 +08:00
KonstantinKondrashov
0f8ff5aa15
efuse: Adds major and minor versions and others
2022-07-05 14:38:27 +08:00
Jakob Hasse
f8b5ed5d6c
refactor (soc, esp_rom)!: removed target-specific ROM dependencies
2022-07-05 13:57:58 +08:00
Omar Chebib
cd48baf979
Refactor: move regi2c_*.h header files from esp_hw_support to soc component
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When creating G0 layer, some regi2c_*.h headers were moved out from
esp_hw_support (G1) to soc (G0). In order to be consistent with that change,
move all the remaining regi2c_*.h headers to soc too.
2022-06-30 09:40:44 +00:00
Armando
31b3f31ef4
ext_mem: make memory region check strict
2022-06-28 14:17:44 +08:00
Mahavir Jain
0a12eab32e
esp_system: move MEMPROT related configuration to soc capability header
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Closes IDF-4506
2022-06-23 10:29:42 +05:30
muhaidong
96f86e0bb4
esp_wifi: esp32c2 does not support wifi mesh
2022-06-21 16:48:52 +08:00
muhaidong
b48b9beace
esp_wifi: esp32c2 does not support csi.
2022-06-20 21:47:51 +08:00
morris
865937fba3
Merge branch 'bugfix/fix_esp32c2_dose_not_support_wapi' into 'master'
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esp_wifi: esp32c2 does not support wapi
Closes IDF-4216
See merge request espressif/esp-idf!18573
2022-06-20 21:31:54 +08:00
muhaidong
2ccce0ca41
esp_wifi: update comments of WI-FI CAPS in soc_caps.h
2022-06-20 19:43:16 +08:00
Martin Vychodil
692b9980b5
Merge branch 'feature/memprot_api_unified_s3_2' into 'master'
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System/Security: Memprot API unified (ESP32S3)
See merge request espressif/esp-idf!16169
2022-06-20 17:34:22 +08:00
muhaidong
6ca2804107
esp_wifi: esp32c2 does not support wapi.
2022-06-20 11:42:12 +08:00
Martin Vychodil
339fcbf14d
System/Security: Memprot API unified (ESP32S3)
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Unified Memory protection API for all PMS-aware chips - ESP32S3 port
2022-06-20 02:36:44 +00:00
Ivan Grokhotkov
3973db7664
soc: make register access macros compatible with C++20
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In C++20, using the result of an assignment to a 'volatile' value is
deprecated.
Breaking change: register "setter" or modification macros can no
longer be used as expressions.
Closes https://github.com/espressif/esp-idf/issues/9170
2022-06-17 18:09:22 +02:00
Omar Chebib
752026a174
Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master'
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G0: RISC-V targets have now an independent G0 layer
See merge request espressif/esp-idf!17926
2022-06-16 11:53:39 +08:00
laokaiyao
28b8fc6a7e
i2s: update documents for driver-NG
2022-06-15 10:30:04 +08:00
Darian
e213e66ba3
Merge branch 'refactor/esp_hw_support_cpu' into 'master'
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esp_hw_support: Add new esp_cpu.h abstraction
Closes IDF-4769
See merge request espressif/esp-idf!17091
2022-06-14 21:11:30 +08:00
Michael (XIAO Xufeng)
7b8e5888ca
Merge branch 'refactor/add_clk_tree_ll' into 'master'
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clk_tree: Stage3 - HAL for clock subsystem
Closes IDF-4334
See merge request espressif/esp-idf!18270
2022-06-14 17:16:29 +08:00
Omar Chebib
5bcd9b2db8
G0: RISC-V targets have now an independent G0 layer
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G0 doesn't depend on any G1+ layer for RISC-V based targets
2022-06-14 15:00:53 +08:00
Darian Leung
61eb7baa6b
esp_hw_support: Add esp_cpu.h abstraction and API
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This commit updates the esp_cpu.h API. The new API presents a new
abstraction of the CPU where CPU presents the following interfaces:
- CPU Control (to stall/unstall/reset the CPU)
- CPU Registers (to read registers commonly used in SW such as SP, PC)
- CPU Interrupts (to inquire/allocate/control the CPUs 32 interrupts)
- Memory Port (to configure the CPU's memory bus for memory protection)
- Debugging (to configure/control the CPU's debugging port)
Note: Also added FORCE_INLINE_ATTR to the DoxyFile in order to pass doc
builds for esp_cpu.h
2022-06-14 14:30:58 +08:00
Konstantin Kondrashov
7d942e0a5d
Merge branch 'feature/efuse_rst_is_treated_as_poweron_rst' into 'master'
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reset_reasons: EFUSE_RST is treated as POWERON_RST + checks errors of eFuse BLOCK0
Closes IDF-3702
See merge request espressif/esp-idf!14742
2022-06-13 21:26:13 +08:00
songruojing
c8752cee6a
clk_tree: Refactor rtc_clk.c by adding HAL layer for clock subsystem
2022-06-13 17:47:50 +08:00
KonstantinKondrashov
46f0313d6b
reset_reasons: EFUSE_RST is treated as POWERON_RST
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ESP32 does not have the EFUSE_RST, the rest chips has this reset reason.
2022-06-09 17:49:03 +08:00
Cao Sen Miao
6589daabb9
MMU: Add configurable mmu page size support on ESP32C2
2022-06-08 19:34:31 +08:00
Geng Yuchao
8012af37d1
Fix soc caps for BT
2022-06-03 21:45:40 +08:00
Konstantin Kondrashov
b824f68b35
Merge branch 'feature/move_dport_workaround_to_g0' into 'master'
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dport_access: Move DPORT workaround to G0
Closes IDF-2177
See merge request espressif/esp-idf!17961
2022-06-01 12:11:12 +08:00
KonstantinKondrashov
c5a4ab39a7
soc: Fix description of efuse fail bits
2022-05-31 11:21:24 +00:00
KonstantinKondrashov
ac4c7d99fe
dport: Move DPORT workaround to G0
2022-05-31 13:44:18 +08:00
Jiang Jiang Jian
2bc5d58807
Merge branch 'feature/support_sleep_for_esp32c2' into 'master'
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esp32c2: support power management
Closes IDF-4440 and IDF-4617
See merge request espressif/esp-idf!18174
2022-05-30 17:57:18 +08:00
Jiang Jiang Jian
0e94779b2e
Merge branch 'feature/support_esp32c2_wifi_new' into 'master'
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Bringup ESP32C2 Wi-Fi
Closes IDF-3905
See merge request espressif/esp-idf!18136
2022-05-29 18:25:24 +08:00
Jiang Jiang Jian
f3922f1b7f
Merge branch 'feature/flash_mmap_refactor' into 'master'
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flash mmap: abstract R/W of MMU table instead of reg access
See merge request espressif/esp-idf!16882
2022-05-29 13:56:37 +08:00
Wu Zheng Hui
b98622c624
efuse: update efuse name
2022-05-28 22:03:16 +08:00
Jessy Chen
7b9b448041
esp_wifi: optimize wifi kconfig
2022-05-28 08:52:55 +00:00
jingli
ae127b04cd
fix ld err since esp32c2 do not suport config gpio of spi flash via efuse
2022-05-27 19:29:38 +08:00