2022-11-22 02:14:51 -05:00
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/*
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2024-01-29 20:40:10 -05:00
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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2022-11-22 02:14:51 -05:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2022-12-06 00:46:03 -05:00
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#include <stdint.h>
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#include <sys/cdefs.h>
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#include <sys/time.h>
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#include <sys/param.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "esp_cpu.h"
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#include "esp_clk_internal.h"
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#include "esp32h2/rom/ets_sys.h"
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#include "esp32h2/rom/uart.h"
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#include "soc/soc.h"
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2023-12-11 04:02:06 -05:00
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#include "soc/pcr_reg.h"
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2022-12-06 00:46:03 -05:00
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#include "soc/rtc.h"
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#include "soc/rtc_periph.h"
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#include "soc/i2s_reg.h"
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2023-12-11 02:27:32 -05:00
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#include "soc/lpperi_reg.h"
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2023-12-14 05:12:09 -05:00
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#include "soc/lp_clkrst_reg.h"
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2023-02-02 01:12:04 -05:00
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#include "soc/pcr_reg.h"
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2022-12-06 00:46:03 -05:00
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#include "hal/wdt_hal.h"
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2023-12-11 04:02:06 -05:00
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#include "hal/uart_ll.h"
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#include "hal/i2c_ll.h"
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#include "hal/rmt_ll.h"
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#include "hal/ledc_ll.h"
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2024-02-28 04:04:18 -05:00
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#include "hal/lp_clkrst_ll.h"
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2023-12-11 04:02:06 -05:00
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#include "hal/timer_ll.h"
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#include "hal/twai_ll.h"
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#include "hal/i2s_ll.h"
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#include "hal/pcnt_ll.h"
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#include "hal/etm_ll.h"
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#include "hal/mcpwm_ll.h"
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#include "hal/parlio_ll.h"
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#include "hal/gdma_ll.h"
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#include "hal/spi_ll.h"
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#include "hal/clk_gate_ll.h"
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#include "hal/temperature_sensor_ll.h"
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2023-12-13 04:37:06 -05:00
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#include "hal/usb_serial_jtag_ll.h"
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#include "hal/usb_fsls_phy_ll.h"
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2022-12-06 00:46:03 -05:00
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#include "esp_private/periph_ctrl.h"
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#include "esp_private/esp_clk.h"
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2023-02-09 02:39:38 -05:00
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#include "esp_private/esp_pmu.h"
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2022-12-06 00:46:03 -05:00
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#include "esp_rom_uart.h"
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#include "esp_rom_sys.h"
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2023-05-28 22:59:24 -04:00
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#include "esp_sleep.h"
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2022-12-06 00:46:03 -05:00
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/* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
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* Larger values increase startup delay. Smaller values may cause false positive
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* detection (i.e. oscillator runs for a few cycles and then stops).
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*/
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#define SLOW_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES
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#define MHZ (1000000)
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2023-01-02 22:00:32 -05:00
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static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src);
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2022-12-06 00:46:03 -05:00
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static const char *TAG = "clk";
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2024-01-29 20:40:10 -05:00
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__attribute__((weak)) void esp_clk_init(void)
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2022-12-06 00:46:03 -05:00
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{
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#if !CONFIG_IDF_ENV_FPGA
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2023-02-09 02:39:38 -05:00
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pmu_init();
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2022-12-06 00:46:03 -05:00
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2024-01-03 02:28:29 -05:00
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assert(rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_32M);
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2022-12-06 00:46:03 -05:00
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2023-02-09 02:39:38 -05:00
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rtc_clk_8m_enable(true);
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2022-12-06 00:46:03 -05:00
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rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
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#endif
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#ifdef CONFIG_BOOTLOADER_WDT_ENABLE
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// WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.
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// If the frequency changes from 150kHz to 32kHz, then the timeout set for the WDT will increase 4.6 times.
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2023-10-23 09:24:56 -04:00
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// Therefore, for the time of frequency change, set a new lower timeout value (2 sec).
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2022-12-06 00:46:03 -05:00
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// This prevents excessive delay before resetting in case the supply voltage is drawdown.
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2023-10-23 09:24:56 -04:00
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// (If frequency is changed from 150kHz to 32kHz then WDT timeout will increased to 2 sec * 150/32 = 9.375 sec).
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2022-12-06 00:46:03 -05:00
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wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &LP_WDT};
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2023-10-23 09:24:56 -04:00
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uint32_t stage_timeout_ticks = (uint32_t)(2000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
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2022-12-06 00:46:03 -05:00
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_feed(&rtc_wdt_ctx);
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//Bootloader has enabled RTC WDT until now. We're only modifying timeout, so keep the stage and timeout action the same
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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#endif
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#if defined(CONFIG_RTC_CLK_SRC_EXT_CRYS)
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2023-01-02 22:00:32 -05:00
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select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_XTAL32K);
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2022-12-06 00:46:03 -05:00
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#elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC)
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2023-01-02 22:00:32 -05:00
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select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_OSC_SLOW);
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#elif defined(CONFIG_RTC_CLK_SRC_INT_RC32K)
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select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_RC32K);
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2022-12-06 00:46:03 -05:00
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#else
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2023-01-02 22:00:32 -05:00
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select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_RC_SLOW);
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2022-12-06 00:46:03 -05:00
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#endif
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#ifdef CONFIG_BOOTLOADER_WDT_ENABLE
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// After changing a frequency WDT timeout needs to be set for new frequency.
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stage_timeout_ticks = (uint32_t)((uint64_t)CONFIG_BOOTLOADER_WDT_TIME_MS * rtc_clk_slow_freq_get_hz() / 1000);
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_feed(&rtc_wdt_ctx);
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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#endif
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rtc_cpu_freq_config_t old_config, new_config;
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rtc_clk_cpu_freq_get_config(&old_config);
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const uint32_t old_freq_mhz = old_config.freq_mhz;
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const uint32_t new_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ;
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bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config);
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assert(res);
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// Wait for UART TX to finish, otherwise some UART output will be lost
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// when switching APB frequency
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2024-01-17 04:19:49 -05:00
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esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
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2022-12-06 00:46:03 -05:00
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if (res) {
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rtc_clk_cpu_freq_set_config(&new_config);
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}
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// Re calculate the ccount to make time calculation correct.
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2024-01-29 20:40:10 -05:00
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esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz);
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2023-02-02 01:12:04 -05:00
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// Set crypto clock (`clk_sec`) to use 96M PLL clock
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REG_SET_FIELD(PCR_SEC_CONF_REG, PCR_SEC_CLK_SEL, 0x3);
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2022-12-06 00:46:03 -05:00
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}
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2023-01-02 22:00:32 -05:00
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static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
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2022-12-06 00:46:03 -05:00
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{
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uint32_t cal_val = 0;
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/* number of times to repeat 32k XTAL calibration
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* before giving up and switching to the internal RC
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*/
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int retry_32k_xtal = 3;
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do {
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2023-02-09 02:39:38 -05:00
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if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K || rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
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2022-12-06 00:46:03 -05:00
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/* 32k XTAL oscillator needs to be enabled and running before it can
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* be used. Hardware doesn't have a direct way of checking if the
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* oscillator is running. Here we use rtc_clk_cal function to count
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* the number of main XTAL cycles in the given number of 32k XTAL
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* oscillator cycles. If the 32k XTAL has not started up, calibration
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* will time out, returning 0.
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*/
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ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
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2023-02-09 02:39:38 -05:00
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rtc_cal_sel_t cal_sel = 0;
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if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
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2022-12-06 00:46:03 -05:00
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rtc_clk_32k_enable(true);
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2023-02-09 02:39:38 -05:00
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cal_sel = RTC_CAL_32K_XTAL;
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} else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
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2022-12-06 00:46:03 -05:00
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rtc_clk_32k_enable_external();
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2023-02-09 02:39:38 -05:00
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cal_sel = RTC_CAL_32K_OSC_SLOW;
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2022-12-06 00:46:03 -05:00
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}
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// When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
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if (SLOW_CLK_CAL_CYCLES > 0) {
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2023-02-09 02:39:38 -05:00
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cal_val = rtc_clk_cal(cal_sel, SLOW_CLK_CAL_CYCLES);
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if (cal_val == 0) {
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2022-12-06 00:46:03 -05:00
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if (retry_32k_xtal-- > 0) {
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continue;
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}
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2023-02-09 02:39:38 -05:00
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ESP_EARLY_LOGW(TAG, "32 kHz clock not found, switching to internal 150 kHz oscillator");
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2022-12-06 00:46:03 -05:00
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rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
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}
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}
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2023-02-09 02:39:38 -05:00
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} else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) {
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rtc_clk_rc32k_enable(true);
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2022-12-06 00:46:03 -05:00
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}
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rtc_clk_slow_src_set(rtc_slow_clk_src);
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if (SLOW_CLK_CAL_CYCLES > 0) {
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/* TODO: 32k XTAL oscillator has some frequency drift at startup.
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* Improve calibration routine to wait until the frequency is stable.
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*/
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cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
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} else {
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const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
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2024-01-29 20:40:10 -05:00
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cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());
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2022-12-06 00:46:03 -05:00
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}
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} while (cal_val == 0);
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2024-03-07 10:43:45 -05:00
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ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %" PRIu32, cal_val);
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2022-12-06 00:46:03 -05:00
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esp_clk_slowclk_cal_set(cal_val);
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}
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void rtc_clk_select_rtc_slow_clk(void)
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{
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2023-01-02 22:00:32 -05:00
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select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_XTAL32K);
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2022-12-06 00:46:03 -05:00
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}
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/* This function is not exposed as an API at this point.
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* All peripheral clocks are default enabled after chip is powered on.
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* This function disables some peripheral clocks when cpu starts.
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* These peripheral clocks are enabled when the peripherals are initialized
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* and disabled when they are de-initialized.
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*/
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__attribute__((weak)) void esp_perip_clk_init(void)
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{
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2023-05-28 22:59:24 -04:00
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soc_rtc_slow_clk_src_t rtc_slow_clk_src = rtc_clk_slow_src_get();
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2024-01-29 20:40:10 -05:00
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esp_sleep_pd_domain_t pu_domain = (esp_sleep_pd_domain_t)(\
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(rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? ESP_PD_DOMAIN_XTAL32K \
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: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) ? ESP_PD_DOMAIN_RC32K \
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: ESP_PD_DOMAIN_MAX);
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2023-05-28 22:59:24 -04:00
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esp_sleep_pd_config(pu_domain, ESP_PD_OPTION_ON);
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2022-12-06 00:46:03 -05:00
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soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
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2023-12-11 04:02:06 -05:00
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if (rst_reason != RESET_REASON_CPU0_MWDT0 && rst_reason != RESET_REASON_CPU0_MWDT1 \
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&& rst_reason != RESET_REASON_CPU0_SW && rst_reason != RESET_REASON_CPU0_RTC_WDT) {
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2022-12-06 00:46:03 -05:00
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#if CONFIG_ESP_CONSOLE_UART_NUM != 0
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2023-12-11 04:02:06 -05:00
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uart_ll_enable_bus_clock(UART_NUM_0, false);
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#elif CONFIG_ESP_CONSOLE_UART_NUM != 1
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uart_ll_enable_bus_clock(UART_NUM_1, false);
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2022-12-06 00:46:03 -05:00
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#endif
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2023-12-11 04:02:06 -05:00
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i2c_ll_enable_bus_clock(0, false);
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i2c_ll_enable_bus_clock(1, false);
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i2c_ll_enable_controller_clock(&I2C0, false);
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i2c_ll_enable_controller_clock(&I2C1, false);
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rmt_ll_enable_bus_clock(0, false);
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rmt_ll_enable_group_clock(0, false);
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ledc_ll_enable_clock(&LEDC, false);
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ledc_ll_enable_bus_clock(false);
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timer_ll_enable_clock(&TIMERG0, 0, false);
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timer_ll_enable_clock(&TIMERG1, 0, false);
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_timer_ll_enable_bus_clock(0, false);
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_timer_ll_enable_bus_clock(1, false);
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twai_ll_enable_clock(0, false);
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twai_ll_enable_bus_clock(0, false);
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i2s_ll_enable_bus_clock(0, false);
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i2s_ll_tx_disable_clock(&I2S0);
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i2s_ll_rx_disable_clock(&I2S0);
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pcnt_ll_enable_bus_clock(0, false);
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etm_ll_enable_bus_clock(0, false);
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mcpwm_ll_enable_bus_clock(0, false);
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mcpwm_ll_group_enable_clock(0, false);
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parlio_ll_rx_enable_clock(&PARL_IO, false);
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parlio_ll_tx_enable_clock(&PARL_IO, false);
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parlio_ll_enable_bus_clock(0, false);
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gdma_ll_force_enable_reg_clock(&GDMA, false);
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gdma_ll_enable_bus_clock(0, false);
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#if CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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spi_ll_enable_bus_clock(SPI1_HOST, false);
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2022-12-06 00:46:03 -05:00
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#endif
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2023-12-11 04:02:06 -05:00
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spi_ll_enable_bus_clock(SPI2_HOST, false);
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temperature_sensor_ll_bus_clk_enable(false);
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periph_ll_disable_clk_set_rst(PERIPH_UHCI0_MODULE);
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periph_ll_disable_clk_set_rst(PERIPH_SARADC_MODULE);
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periph_ll_disable_clk_set_rst(PERIPH_REGDMA_MODULE);
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2023-12-11 03:16:43 -05:00
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#if !CONFIG_ESP_SYSTEM_HW_PC_RECORD
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/* Disable ASSIST Debug module clock if PC recoreding function is not used,
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* if stack guard function needs it, it will be re-enabled at esp_hw_stack_guard_init */
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2023-12-11 04:02:06 -05:00
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periph_ll_disable_clk_set_rst(PERIPH_ASSIST_DEBUG_MODULE);
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2022-12-06 00:46:03 -05:00
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#endif
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2023-12-11 04:02:06 -05:00
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periph_ll_disable_clk_set_rst(PERIPH_RSA_MODULE);
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periph_ll_disable_clk_set_rst(PERIPH_AES_MODULE);
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periph_ll_disable_clk_set_rst(PERIPH_SHA_MODULE);
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periph_ll_disable_clk_set_rst(PERIPH_ECC_MODULE);
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periph_ll_disable_clk_set_rst(PERIPH_HMAC_MODULE);
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periph_ll_disable_clk_set_rst(PERIPH_DS_MODULE);
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periph_ll_disable_clk_set_rst(PERIPH_ECDSA_MODULE);
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// TODO: Replace with hal implementation
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2023-12-13 06:18:27 -05:00
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REG_CLR_BIT(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE);
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2023-12-11 04:02:06 -05:00
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REG_CLR_BIT(PCR_TRACE_CONF_REG, PCR_TRACE_CLK_EN);
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REG_CLR_BIT(PCR_MEM_MONITOR_CONF_REG, PCR_MEM_MONITOR_CLK_EN);
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REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
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REG_CLR_BIT(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
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2023-12-14 05:12:09 -05:00
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WRITE_PERI_REG(PCR_CTRL_CLK_OUT_EN_REG, 0);
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2023-12-13 04:37:06 -05:00
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#if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
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// Disable USB-Serial-JTAG clock and it's pad if not used
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usb_fsls_phy_ll_int_jtag_disable(&USB_SERIAL_JTAG);
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usb_serial_jtag_ll_enable_bus_clock(false);
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2022-12-06 00:46:03 -05:00
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#endif
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}
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2023-12-11 02:27:32 -05:00
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if (rst_reason == RESET_REASON_CHIP_POWER_ON || rst_reason == RESET_REASON_CHIP_BROWN_OUT \
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|| rst_reason == RESET_REASON_SYS_RTC_WDT || rst_reason == RESET_REASON_SYS_SUPER_WDT) {
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2024-02-28 04:04:18 -05:00
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_lp_clkrst_ll_enable_rng_clock(false);
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2023-12-11 02:27:32 -05:00
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CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_OTP_DBG_CK_EN);
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CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_ANA_I2C_CK_EN);
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CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_IO_CK_EN);
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2023-12-14 05:12:09 -05:00
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WRITE_PERI_REG(LP_CLKRST_LP_CLK_PO_EN_REG, 0);
|
2023-12-11 02:27:32 -05:00
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}
|
2022-12-06 00:46:03 -05:00
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}
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