esp-idf/components/riscv/include/esp_private/panic_reason.h

/*
 * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#pragma once

#include "soc/soc_caps.h"

/* Need a way to signal which core caused the INT WDT like we do with EXCAUSE on xtensa.
   Choosing a large number that is unlikely to conflict with any actual riscv mcauses
   bit 12 and above are always zero on the CPU used by P4
 */
#define PANIC_RSN_INTWDT_CPU0 ETS_INT_WDT_INUM
#if SOC_CPU_CORES_NUM > 1
#define PANIC_RSN_INTWDT_CPU1_FLAG (1 << 12)
#define PANIC_RSN_INTWDT_CPU1 (PANIC_RSN_INTWDT_CPU1_FLAG | ETS_INT_WDT_INUM)
#endif

#define PANIC_RSN_CACHEERR    3

#define MCAUSE_ILLIGAL_INSTRUCTION_ACCESS    1
#define MCAUSE_ILLEGAL_INSTRUCTION           2
#define MCAUSE_LOAD_ACCESS_FAULT             5
riscv: fix panic_reasons being an instance of enum, not type name 2022-01-14 12:05:01 -05:00			`/*`
feat(panic): base support on p4 2023-07-19 04:28:03 -04:00			`* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD`
riscv: fix panic_reasons being an instance of enum, not type name 2022-01-14 12:05:01 -05:00			`*`
			`* SPDX-License-Identifier: Apache-2.0`
			`*/`
esp_system: support riscv panic 2020-10-08 01:18:16 -04:00			`#pragma once`

feat(wdt): add multicore support for WDTs on RISCV 2023-08-31 00:19:49 -04:00			`#include "soc/soc_caps.h"`

			`/* Need a way to signal which core caused the INT WDT like we do with EXCAUSE on xtensa.`
			`Choosing a large number that is unlikely to conflict with any actual riscv mcauses`
			`bit 12 and above are always zero on the CPU used by P4`
feat(esp_system): implement hw stack guard for riscv chips - add hardware stack guard based on assist-debug module - enable hardware stack guard by default - disable hardware stack guard for freertos ci.release test - refactor rtos_int_enter/rtos_int_exit to change SP register inside them - fix panic_reason.h header for RISC-V - update docs to include information about the new feature 2023-05-04 11:31:31 -04:00			`*/`
			`#define PANIC_RSN_INTWDT_CPU0 ETS_INT_WDT_INUM`
feat(panic): base support on p4 2023-07-19 04:28:03 -04:00			`#if SOC_CPU_CORES_NUM > 1`
feat(wdt): add multicore support for WDTs on RISCV 2023-08-31 00:19:49 -04:00			`#define PANIC_RSN_INTWDT_CPU1_FLAG (1 << 12)`
			`#define PANIC_RSN_INTWDT_CPU1 (PANIC_RSN_INTWDT_CPU1_FLAG \| ETS_INT_WDT_INUM)`
feat(panic): base support on p4 2023-07-19 04:28:03 -04:00			`#endif`
feat(wdt): add multicore support for WDTs on RISCV 2023-08-31 00:19:49 -04:00
feat(panic): base support on p4 2023-07-19 04:28:03 -04:00			`#define PANIC_RSN_CACHEERR 3`
fix(panic): fixed cache error being reported as illegal instruction On riscv chips accessing cache mapped memory regions over the ibus would result in an illegal instructions exception triggering faster than the cache error interrupt/exception. Added a cache error check in the panic handler, if any cache errors are active the panic handler will now report a cache error, even if the trigger exception was a illegal instructions. 2023-11-27 20:57:44 -05:00
feat(panic): supported more cache error cactch 2024-07-11 03:23:29 -04:00			`#define MCAUSE_ILLIGAL_INSTRUCTION_ACCESS 1`
			`#define MCAUSE_ILLEGAL_INSTRUCTION 2`
			`#define MCAUSE_LOAD_ACCESS_FAULT 5`