esp-idf/components/riscv/include/esp_private/panic_reason.h

/*
 * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#pragma once

/* Since riscv does not replace mcause with "pseudo_reason" as it xtensa does
 * PANIC_RSN_* defined with original interrupt numbers to make it work in
 * common code
 */
#define PANIC_RSN_INTWDT_CPU0 ETS_INT_WDT_INUM

//TODO: IDF-7511
#if SOC_CPU_CORES_NUM > 1
#define PANIC_RSN_INTWDT_CPU1 ETS_INT_WDT_INUM
#endif
#define PANIC_RSN_CACHEERR    3
riscv: fix panic_reasons being an instance of enum, not type name 2022-01-14 12:05:01 -05:00			`/*`
feat(panic): base support on p4 2023-07-19 04:28:03 -04:00			`* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD`
riscv: fix panic_reasons being an instance of enum, not type name 2022-01-14 12:05:01 -05:00			`*`
			`* SPDX-License-Identifier: Apache-2.0`
			`*/`
esp_system: support riscv panic 2020-10-08 01:18:16 -04:00			`#pragma once`

feat(esp_system): implement hw stack guard for riscv chips - add hardware stack guard based on assist-debug module - enable hardware stack guard by default - disable hardware stack guard for freertos ci.release test - refactor rtos_int_enter/rtos_int_exit to change SP register inside them - fix panic_reason.h header for RISC-V - update docs to include information about the new feature 2023-05-04 11:31:31 -04:00			`/* Since riscv does not replace mcause with "pseudo_reason" as it xtensa does`
			`* PANIC_RSN_* defined with original interrupt numbers to make it work in`
			`* common code`
			`*/`
			`#define PANIC_RSN_INTWDT_CPU0 ETS_INT_WDT_INUM`
feat(panic): base support on p4 2023-07-19 04:28:03 -04:00
			`//TODO: IDF-7511`
			`#if SOC_CPU_CORES_NUM > 1`
			`#define PANIC_RSN_INTWDT_CPU1 ETS_INT_WDT_INUM`
			`#endif`
			`#define PANIC_RSN_CACHEERR 3`