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25 lines
778 B
C
25 lines
778 B
C
/*
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "soc/soc_caps.h"
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/* Need a way to signal which core caused the INT WDT like we do with EXCAUSE on xtensa.
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Choosing a large number that is unlikely to conflict with any actual riscv mcauses
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bit 12 and above are always zero on the CPU used by P4
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*/
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#define PANIC_RSN_INTWDT_CPU0 ETS_INT_WDT_INUM
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#if SOC_CPU_CORES_NUM > 1
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#define PANIC_RSN_INTWDT_CPU1_FLAG (1 << 12)
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#define PANIC_RSN_INTWDT_CPU1 (PANIC_RSN_INTWDT_CPU1_FLAG | ETS_INT_WDT_INUM)
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#endif
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#define PANIC_RSN_CACHEERR 3
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#define MCAUSE_ILLIGAL_INSTRUCTION_ACCESS 1
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#define MCAUSE_ILLEGAL_INSTRUCTION 2
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#define MCAUSE_LOAD_ACCESS_FAULT 5
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