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feat(panic): supported more cache error cactch
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@ -39,7 +39,6 @@
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*/
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static inline void print_cache_err_details(const void *frame)
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{
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#if !CONFIG_IDF_TARGET_ESP32P4
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const char* cache_err_msg = esp_cache_err_panic_string();
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if (cache_err_msg) {
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panic_print_str(cache_err_msg);
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@ -47,7 +46,6 @@ static inline void print_cache_err_details(const void *frame)
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panic_print_str("Cache error active, but failed to find a corresponding error message");
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}
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panic_print_str("\r\n");
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#endif
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}
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#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
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@ -195,7 +193,7 @@ bool panic_soc_check_pseudo_cause(void *f, panic_info_t *info)
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/* Cache errors when reading instructions will result in an illegal instructions,
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before any cache error interrupts trigger. We override the exception cause if
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any cache errors are active to more accurately report the actual reason */
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if (esp_cache_err_has_active_err() && (frame->mcause == MCAUSE_ILLEGAL_INSTRUCTION)) {
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if (esp_cache_err_has_active_err() && ((frame->mcause == MCAUSE_ILLEGAL_INSTRUCTION) || (frame->mcause == MCAUSE_ILLIGAL_INSTRUCTION_ACCESS) || (frame->mcause == MCAUSE_LOAD_ACCESS_FAULT))) {
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pseudo_cause = true;
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frame->mcause = ETS_CACHEERR_INUM;
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}
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@ -19,4 +19,6 @@
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#define PANIC_RSN_CACHEERR 3
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#define MCAUSE_ILLEGAL_INSTRUCTION 2
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#define MCAUSE_ILLIGAL_INSTRUCTION_ACCESS 1
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#define MCAUSE_ILLEGAL_INSTRUCTION 2
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#define MCAUSE_LOAD_ACCESS_FAULT 5
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