esp-idf/components/riscv/include/riscv
Darian Leung 61eb7baa6b esp_hw_support: Add esp_cpu.h abstraction and API
This commit updates the esp_cpu.h API. The new API presents a new
abstraction of the CPU where CPU presents the following interfaces:

- CPU Control (to stall/unstall/reset the CPU)
- CPU Registers (to read registers commonly used in SW such as SP, PC)
- CPU Interrupts (to inquire/allocate/control the CPUs 32 interrupts)
- Memory Port (to configure the CPU's memory bus for memory protection)
- Debugging (to configure/control the CPU's debugging port)

Note: Also added FORCE_INLINE_ATTR to the DoxyFile in order to pass doc
        builds for esp_cpu.h
2022-06-14 14:30:58 +08:00
..
csr.h ESP8684: add soc, riscv, newlib support 2021-11-06 17:33:44 +08:00
encoding.h riscv: Add new arch-level component 2020-11-12 09:33:18 +11:00
instruction_decode.h interrupt: filter out reserved int number by decoding risc-v JAL instruction 2021-01-05 15:39:46 +08:00
interrupt.h esp_hw_support: Add esp_cpu.h abstraction and API 2022-06-14 14:30:58 +08:00
riscv_interrupts.h riscv: Add new arch-level component 2020-11-12 09:33:18 +11:00
rv_utils.h esp_hw_support: Add esp_cpu.h abstraction and API 2022-06-14 14:30:58 +08:00
rvruntime-frames.h esp_system: support riscv panic 2020-11-13 07:49:11 +11:00
semihosting.h semihosting: version 2 2022-05-05 09:12:42 +00:00