Wangjialin 2b986fbd49 For esp_restart API, reset uart0 core first, then reset uart0 apb side, so as to prevent uart output garbage after cpu reset. (UART0 RST bits will be cleared in ROM) ... Add UART0/1 core reset on esp32c3, in case uart driver would also reset uart hardwares.		2021-07-21 11:41:04 +08:00
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esp32	soc: add reset reasons in soc component	2021-07-13 10:45:38 +08:00
esp32c3	For esp_restart API, reset uart0 core first, then reset uart0 apb side, so as to prevent uart output garbage after cpu reset. (UART0 RST bits will be cleared in ROM)	2021-07-21 11:41:04 +08:00
esp32h2	soc: add reset reasons in soc component	2021-07-13 10:45:38 +08:00
esp32s2	esp32s2: FPGA can boot to Hello World	2021-07-16 10:50:06 +10:00
esp32s3	soc: add reset reasons in soc component	2021-07-13 10:45:38 +08:00