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esp-idf/components/efuse/esp32/esp_efuse_table.csv

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# field_name, | efuse_block, | bit_start, | bit_count, |comment #
# | (EFUSE_BLK0 | (0..255) | (1-256) | #
# | EFUSE_BLK1 | | | #
# | ...) | | | #
##########################################################################
# !!!!!!!!!!! #
# After editing this file, run the command manually "idf.py efuse-common-table"
# this will generate new source files, next rebuild all the sources.
# !!!!!!!!!!! #
# This file was generated by regtools.py based on the efuses.yaml file with the version: 369d2d860d34e777c0f7d545a7dfc3c4
WR_DIS, EFUSE_BLK0, 0, 16, [] Efuse write disable mask
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [WR_DIS.EFUSE_RD_DISABLE] wr_dis of RD_DIS
WR_DIS.WR_DIS, EFUSE_BLK0, 1, 1, [] wr_dis of WR_DIS
WR_DIS.FLASH_CRYPT_CNT, EFUSE_BLK0, 2, 1, [] wr_dis of FLASH_CRYPT_CNT
WR_DIS.UART_DOWNLOAD_DIS, EFUSE_BLK0, 2, 1, [] wr_dis of UART_DOWNLOAD_DIS
WR_DIS.MAC, EFUSE_BLK0, 3, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
WR_DIS.MAC_CRC, EFUSE_BLK0, 3, 1, [WR_DIS.MAC_FACTORY_CRC] wr_dis of MAC_CRC
WR_DIS.DISABLE_APP_CPU, EFUSE_BLK0, 3, 1, [WR_DIS.CHIP_VER_DIS_APP_CPU] wr_dis of DISABLE_APP_CPU
WR_DIS.DISABLE_BT, EFUSE_BLK0, 3, 1, [WR_DIS.CHIP_VER_DIS_BT] wr_dis of DISABLE_BT
WR_DIS.DIS_CACHE, EFUSE_BLK0, 3, 1, [WR_DIS.CHIP_VER_DIS_CACHE] wr_dis of DIS_CACHE
WR_DIS.VOL_LEVEL_HP_INV, EFUSE_BLK0, 3, 1, [] wr_dis of VOL_LEVEL_HP_INV
WR_DIS.CLK8M_FREQ, EFUSE_BLK0, 4, 1, [WR_DIS.CK8M_FREQ] wr_dis of CLK8M_FREQ
WR_DIS.ADC_VREF, EFUSE_BLK0, 4, 1, [] wr_dis of ADC_VREF
WR_DIS.XPD_SDIO_REG, EFUSE_BLK0, 5, 1, [] wr_dis of XPD_SDIO_REG
WR_DIS.XPD_SDIO_TIEH, EFUSE_BLK0, 5, 1, [WR_DIS.SDIO_TIEH] wr_dis of XPD_SDIO_TIEH
WR_DIS.XPD_SDIO_FORCE, EFUSE_BLK0, 5, 1, [WR_DIS.SDIO_FORCE] wr_dis of XPD_SDIO_FORCE
WR_DIS.SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 6, 1, [] wr_dis of SPI_PAD_CONFIG_CLK
WR_DIS.SPI_PAD_CONFIG_Q, EFUSE_BLK0, 6, 1, [] wr_dis of SPI_PAD_CONFIG_Q
WR_DIS.SPI_PAD_CONFIG_D, EFUSE_BLK0, 6, 1, [] wr_dis of SPI_PAD_CONFIG_D
WR_DIS.SPI_PAD_CONFIG_CS0, EFUSE_BLK0, 6, 1, [] wr_dis of SPI_PAD_CONFIG_CS0
WR_DIS.BLOCK1, EFUSE_BLK0, 7, 1, [WR_DIS.ENCRYPT_FLASH_KEY WR_DIS.BLK1] wr_dis of BLOCK1
WR_DIS.BLOCK2, EFUSE_BLK0, 8, 1, [WR_DIS.SECURE_BOOT_KEY WR_DIS.BLK2] wr_dis of BLOCK2
WR_DIS.BLOCK3, EFUSE_BLK0, 9, 1, [WR_DIS.BLK3] wr_dis of BLOCK3
WR_DIS.CUSTOM_MAC_CRC, EFUSE_BLK0, 9, 1, [WR_DIS.MAC_CUSTOM_CRC] wr_dis of CUSTOM_MAC_CRC
WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 9, 1, [WR_DIS.MAC_CUSTOM] wr_dis of CUSTOM_MAC
WR_DIS.ADC1_TP_LOW, EFUSE_BLK0, 9, 1, [] wr_dis of ADC1_TP_LOW
WR_DIS.ADC1_TP_HIGH, EFUSE_BLK0, 9, 1, [] wr_dis of ADC1_TP_HIGH
WR_DIS.ADC2_TP_LOW, EFUSE_BLK0, 9, 1, [] wr_dis of ADC2_TP_LOW
WR_DIS.ADC2_TP_HIGH, EFUSE_BLK0, 9, 1, [] wr_dis of ADC2_TP_HIGH
WR_DIS.SECURE_VERSION, EFUSE_BLK0, 9, 1, [] wr_dis of SECURE_VERSION
WR_DIS.MAC_VERSION, EFUSE_BLK0, 9, 1, [WR_DIS.MAC_CUSTOM_VER] wr_dis of MAC_VERSION
WR_DIS.BLK3_PART_RESERVE, EFUSE_BLK0, 10, 1, [] wr_dis of BLK3_PART_RESERVE
WR_DIS.FLASH_CRYPT_CONFIG, EFUSE_BLK0, 10, 1, [WR_DIS.ENCRYPT_CONFIG] wr_dis of FLASH_CRYPT_CONFIG
WR_DIS.CODING_SCHEME, EFUSE_BLK0, 10, 1, [] wr_dis of CODING_SCHEME
WR_DIS.KEY_STATUS, EFUSE_BLK0, 10, 1, [] wr_dis of KEY_STATUS
WR_DIS.ABS_DONE_0, EFUSE_BLK0, 12, 1, [] wr_dis of ABS_DONE_0
WR_DIS.ABS_DONE_1, EFUSE_BLK0, 13, 1, [] wr_dis of ABS_DONE_1
WR_DIS.JTAG_DISABLE, EFUSE_BLK0, 14, 1, [WR_DIS.DISABLE_JTAG] wr_dis of JTAG_DISABLE
WR_DIS.CONSOLE_DEBUG_DISABLE, EFUSE_BLK0, 15, 1, [] wr_dis of CONSOLE_DEBUG_DISABLE
WR_DIS.DISABLE_DL_ENCRYPT, EFUSE_BLK0, 15, 1, [] wr_dis of DISABLE_DL_ENCRYPT
WR_DIS.DISABLE_DL_DECRYPT, EFUSE_BLK0, 15, 1, [] wr_dis of DISABLE_DL_DECRYPT
WR_DIS.DISABLE_DL_CACHE, EFUSE_BLK0, 15, 1, [] wr_dis of DISABLE_DL_CACHE
RD_DIS, EFUSE_BLK0, 16, 4, [] Disable reading from BlOCK1-3
RD_DIS.BLOCK1, EFUSE_BLK0, 16, 1, [RD_DIS.ENCRYPT_FLASH_KEY RD_DIS.BLK1] rd_dis of BLOCK1
RD_DIS.BLOCK2, EFUSE_BLK0, 17, 1, [RD_DIS.SECURE_BOOT_KEY RD_DIS.BLK2] rd_dis of BLOCK2
RD_DIS.BLOCK3, EFUSE_BLK0, 18, 1, [RD_DIS.BLK3] rd_dis of BLOCK3
RD_DIS.CUSTOM_MAC_CRC, EFUSE_BLK0, 18, 1, [RD_DIS.MAC_CUSTOM_CRC] rd_dis of CUSTOM_MAC_CRC
RD_DIS.CUSTOM_MAC, EFUSE_BLK0, 18, 1, [RD_DIS.MAC_CUSTOM] rd_dis of CUSTOM_MAC
RD_DIS.ADC1_TP_LOW, EFUSE_BLK0, 18, 1, [] rd_dis of ADC1_TP_LOW
RD_DIS.ADC1_TP_HIGH, EFUSE_BLK0, 18, 1, [] rd_dis of ADC1_TP_HIGH
RD_DIS.ADC2_TP_LOW, EFUSE_BLK0, 18, 1, [] rd_dis of ADC2_TP_LOW
RD_DIS.ADC2_TP_HIGH, EFUSE_BLK0, 18, 1, [] rd_dis of ADC2_TP_HIGH
RD_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] rd_dis of SECURE_VERSION
RD_DIS.MAC_VERSION, EFUSE_BLK0, 18, 1, [RD_DIS.MAC_CUSTOM_VER] rd_dis of MAC_VERSION
RD_DIS.BLK3_PART_RESERVE, EFUSE_BLK0, 19, 1, [] rd_dis of BLK3_PART_RESERVE
RD_DIS.FLASH_CRYPT_CONFIG, EFUSE_BLK0, 19, 1, [RD_DIS.ENCRYPT_CONFIG] rd_dis of FLASH_CRYPT_CONFIG
RD_DIS.CODING_SCHEME, EFUSE_BLK0, 19, 1, [] rd_dis of CODING_SCHEME
RD_DIS.KEY_STATUS, EFUSE_BLK0, 19, 1, [] rd_dis of KEY_STATUS
FLASH_CRYPT_CNT, EFUSE_BLK0, 20, 7, [] Flash encryption is enabled if this field has an odd number of bits set
UART_DOWNLOAD_DIS, EFUSE_BLK0, 27, 1, [] Disable UART download mode. Valid for ESP32 V3 and newer; only
MAC, EFUSE_BLK0, 72, 8, [MAC_FACTORY] MAC address
, EFUSE_BLK0, 64, 8, [MAC_FACTORY] MAC address
, EFUSE_BLK0, 56, 8, [MAC_FACTORY] MAC address
, EFUSE_BLK0, 48, 8, [MAC_FACTORY] MAC address
, EFUSE_BLK0, 40, 8, [MAC_FACTORY] MAC address
, EFUSE_BLK0, 32, 8, [MAC_FACTORY] MAC address
MAC_CRC, EFUSE_BLK0, 80, 8, [MAC_FACTORY_CRC] CRC8 for MAC address
DISABLE_APP_CPU, EFUSE_BLK0, 96, 1, [CHIP_VER_DIS_APP_CPU] Disables APP CPU
DISABLE_BT, EFUSE_BLK0, 97, 1, [CHIP_VER_DIS_BT] Disables Bluetooth
CHIP_PACKAGE_4BIT, EFUSE_BLK0, 98, 1, [CHIP_VER_PKG_4BIT] Chip package identifier #4bit
DIS_CACHE, EFUSE_BLK0, 99, 1, [CHIP_VER_DIS_CACHE] Disables cache
SPI_PAD_CONFIG_HD, EFUSE_BLK0, 100, 5, [] read for SPI_pad_config_hd
CHIP_PACKAGE, EFUSE_BLK0, 105, 3, [CHIP_VER_PKG] Chip package identifier
CHIP_CPU_FREQ_LOW, EFUSE_BLK0, 108, 1, [] If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED; the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise
CHIP_CPU_FREQ_RATED, EFUSE_BLK0, 109, 1, [] If set; the ESP32's maximum CPU frequency has been rated
BLK3_PART_RESERVE, EFUSE_BLK0, 110, 1, [] BLOCK3 partially served for ADC calibration data
CHIP_VER_REV1, EFUSE_BLK0, 111, 1, [] bit is set to 1 for rev1 silicon
CLK8M_FREQ, EFUSE_BLK0, 128, 8, [CK8M_FREQ] 8MHz clock freq override
ADC_VREF, EFUSE_BLK0, 136, 5, [] True ADC reference voltage
XPD_SDIO_REG, EFUSE_BLK0, 142, 1, [] read for XPD_SDIO_REG
XPD_SDIO_TIEH, EFUSE_BLK0, 143, 1, [SDIO_TIEH] If XPD_SDIO_FORCE & XPD_SDIO_REG {1: "3.3V"; 0: "1.8V"}
XPD_SDIO_FORCE, EFUSE_BLK0, 144, 1, [SDIO_FORCE] Ignore MTDI pin (GPIO12) for VDD_SDIO on reset
SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 160, 5, [] Override SD_CLK pad (GPIO6/SPICLK)
SPI_PAD_CONFIG_Q, EFUSE_BLK0, 165, 5, [] Override SD_DATA_0 pad (GPIO7/SPIQ)
SPI_PAD_CONFIG_D, EFUSE_BLK0, 170, 5, [] Override SD_DATA_1 pad (GPIO8/SPID)
SPI_PAD_CONFIG_CS0, EFUSE_BLK0, 175, 5, [] Override SD_CMD pad (GPIO11/SPICS0)
CHIP_VER_REV2, EFUSE_BLK0, 180, 1, []
VOL_LEVEL_HP_INV, EFUSE_BLK0, 182, 2, [] This field stores the voltage level for CPU to run at 240 MHz; or for flash/PSRAM to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)
WAFER_VERSION_MINOR, EFUSE_BLK0, 184, 2, []
FLASH_CRYPT_CONFIG, EFUSE_BLK0, 188, 4, [ENCRYPT_CONFIG] Flash encryption config (key tweak bits)
CODING_SCHEME, EFUSE_BLK0, 192, 2, [] Efuse variable block length scheme {0: "NONE (BLK1-3 len=256 bits)"; 1: "3/4 (BLK1-3 len=192 bits)"; 2: "REPEAT (BLK1-3 len=128 bits) not supported"; 3: "NONE (BLK1-3 len=256 bits)"}
CONSOLE_DEBUG_DISABLE, EFUSE_BLK0, 194, 1, [] Disable ROM BASIC interpreter fallback
DISABLE_SDIO_HOST, EFUSE_BLK0, 195, 1, []
ABS_DONE_0, EFUSE_BLK0, 196, 1, [] Secure boot V1 is enabled for bootloader image
ABS_DONE_1, EFUSE_BLK0, 197, 1, [] Secure boot V2 is enabled for bootloader image
JTAG_DISABLE, EFUSE_BLK0, 198, 1, [DISABLE_JTAG] Disable JTAG
DISABLE_DL_ENCRYPT, EFUSE_BLK0, 199, 1, [] Disable flash encryption in UART bootloader
DISABLE_DL_DECRYPT, EFUSE_BLK0, 200, 1, [] Disable flash decryption in UART bootloader
DISABLE_DL_CACHE, EFUSE_BLK0, 201, 1, [] Disable flash cache in UART bootloader
KEY_STATUS, EFUSE_BLK0, 202, 1, [] Usage of efuse block 3 (reserved)
BLOCK1, EFUSE_BLK1, 0, MAX_BLK_LEN, [ENCRYPT_FLASH_KEY] Flash encryption key
BLOCK2, EFUSE_BLK2, 0, MAX_BLK_LEN, [SECURE_BOOT_KEY] Security boot key
CUSTOM_MAC_CRC, EFUSE_BLK3, 0, 8, [MAC_CUSTOM_CRC] CRC8 for custom MAC address
MAC_CUSTOM, EFUSE_BLK3, 8, 48, [MAC_CUSTOM] Custom MAC address
ADC1_TP_LOW, EFUSE_BLK3, 96, 7, [] ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE
ADC1_TP_HIGH, EFUSE_BLK3, 103, 9, [] ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE
ADC2_TP_LOW, EFUSE_BLK3, 112, 7, [] ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE
ADC2_TP_HIGH, EFUSE_BLK3, 119, 9, [] ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE
SECURE_VERSION, EFUSE_BLK3, 128, 32, [] Secure version for anti-rollback
MAC_VERSION, EFUSE_BLK3, 184, 8, [MAC_CUSTOM_VER] Version of the MAC field {1: "Custom MAC in BLOCK3"}
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