esp-idf/components/soc
2024-02-21 11:59:28 +08:00
..
esp32 refactor(uart): add support to be able to test LP_UART port 2024-02-07 14:37:48 +08:00
esp32c2 refactor(uart): add support to be able to test LP_UART port 2024-02-07 14:37:48 +08:00
esp32c3 refactor(uart): add support to be able to test LP_UART port 2024-02-07 14:37:48 +08:00
esp32c5 fix(system): update reset reasons for P4 and C5 2024-02-21 11:59:28 +08:00
esp32c6 fix(system): update reset reasons for C6 and H2 2024-02-20 12:27:09 +08:00
esp32h2 fix(system): update reset reasons for C6 and H2 2024-02-20 12:27:09 +08:00
esp32p4 fix(system): update reset reasons for P4 and C5 2024-02-21 11:59:28 +08:00
esp32s2 refactor(uart): add support to be able to test LP_UART port 2024-02-07 14:37:48 +08:00
esp32s3 refactor(uart): add support to be able to test LP_UART port 2024-02-07 14:37:48 +08:00
include/soc Merge branch 'feat/csi_driver' into 'master' 2024-02-05 09:59:35 +08:00
linux/include/soc feat(esp32c5): support esp32c5 g0 components 2023-12-08 15:12:24 +08:00
CMakeLists.txt feat(csi): added csi driver 2024-02-04 19:06:11 +08:00
dport_access_common.c dport: Move DPORT workaround to G0 2022-05-31 13:44:18 +08:00
Kconfig mmu: support configurable mmu page size 2023-03-04 02:48:40 +00:00
linker.lf soc: move implementations to esp_hw_support 2020-10-28 22:38:50 +08:00
lldesc.c crypto: initial S3 Beta 3 bringup and testing for SHA/AES/RSA/flash enc 2021-05-18 11:25:41 +08:00
README.md soc: descriptive part occupy whole component 2020-10-28 07:21:29 +08:00

soc

The soc component provides hardware description for targets supported by ESP-IDF.

- `xxx_reg.h`   - defines registers related to the hardware
- `xxx_struct.h` - hardware description in C `struct`
- `xxx_channel.h` - definitions for hardware with multiple channels
- `xxx_caps.h`  - features/capabilities of the hardware
- `xxx_pins.h`  - pin definitions
- `xxx_periph.h/*.c`  - includes all headers related to a peripheral; declaration and definition of IO mapping for that hardware