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a8f509f481
- As the PMA entry that made some memory regions cacheable was assigned the highest priority, some intermediate inaccessible memory regions bypassed protection. - Added tests for the same - Verified that even after changing the priority of the PMA entry, a write operation at SOC_IRAM_LOW + 0x40 (a random RAM cached address) still needs the same number (29) of CPU cycles. |
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.. | ||
include | ||
panic_utils | ||
CMakeLists.txt | ||
Kconfig.projbuild | ||
test_app_main.c | ||
test_memprot.c | ||
test_panic.c |