mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
a8f509f481
- As the PMA entry that made some memory regions cacheable was assigned the highest priority, some intermediate inaccessible memory regions bypassed protection. - Added tests for the same - Verified that even after changing the priority of the PMA entry, a write operation at SOC_IRAM_LOW + 0x40 (a random RAM cached address) still needs the same number (29) of CPU cycles.
179 lines
5.6 KiB
C
179 lines
5.6 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdio.h>
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#include <unistd.h>
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#include <assert.h>
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#include <string.h>
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#include "esp_err.h"
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#include "esp_system.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "test_panic.h"
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#include "test_memprot.h"
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/* Test Utility Functions */
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#define BOOT_CMD_MAX_LEN (128)
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#define HANDLE_TEST(test_name, name_) \
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if (strcmp(test_name, #name_) == 0) { \
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name_(); \
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die("Test function has returned"); \
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}
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static const char* get_test_name(void)
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{
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static char test_name_str[BOOT_CMD_MAX_LEN] = {0};
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bool print_prompt = true;
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/* Not using blocking fgets(stdin) here, as QEMU doesn't yet implement RX timeout interrupt,
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* which is required for the UART driver and blocking stdio to work.
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*/
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int c = EOF;
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char *p = test_name_str;
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const char *end = test_name_str + sizeof(test_name_str) - 1;
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while (p < end) {
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if (print_prompt) {
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printf("Enter test name: ");
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fflush(stdout);
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print_prompt = false;
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}
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c = getchar();
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if (c == EOF) {
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vTaskDelay(pdMS_TO_TICKS(10));
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} else if (c == '\r' || c == '\n') {
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/* terminate the line */
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puts("\n\r");
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fflush(stdout);
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print_prompt = true;
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if (p != test_name_str) {
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*p = '\0';
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break;
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}
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} else if (c >= '0' && c <= 'z') {
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/* echo the received character */
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putchar(c);
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fflush(stdout);
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/* and save it */
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*p = c;
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++p;
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}
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}
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return test_name_str;
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}
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/* app_main */
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void app_main(void)
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{
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/* Needed to allow the tick hook to set correct INT WDT timeouts */
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vTaskDelay(2);
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/* Test script sends to command over UART. Read it and determine how to proceed. */
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const char* test_name = get_test_name();
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if (test_name == NULL) {
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/* Nothing to do */
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return;
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}
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printf("Got test name: %s\n", test_name);
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HANDLE_TEST(test_name, test_abort);
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HANDLE_TEST(test_name, test_abort_cache_disabled);
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HANDLE_TEST(test_name, test_int_wdt);
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HANDLE_TEST(test_name, test_task_wdt_cpu0);
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#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
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HANDLE_TEST(test_name, test_hw_stack_guard_cpu0);
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#if !CONFIG_FREERTOS_UNICORE
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HANDLE_TEST(test_name, test_hw_stack_guard_cpu1);
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#endif // CONFIG_FREERTOS_UNICORE
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#endif // CONFIG_ESP_SYSTEM_HW_STACK_GUARD
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#if CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
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HANDLE_TEST(test_name, test_panic_extram_stack_heap);
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#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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HANDLE_TEST(test_name, test_panic_extram_stack_bss);
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#endif
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#endif
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#if CONFIG_ESP_COREDUMP_CAPTURE_DRAM
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HANDLE_TEST(test_name, test_capture_dram);
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#endif
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#if !CONFIG_FREERTOS_UNICORE
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HANDLE_TEST(test_name, test_task_wdt_cpu1);
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#endif
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HANDLE_TEST(test_name, test_loadprohibited);
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HANDLE_TEST(test_name, test_storeprohibited);
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HANDLE_TEST(test_name, test_cache_error);
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HANDLE_TEST(test_name, test_int_wdt_cache_disabled);
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HANDLE_TEST(test_name, test_stack_overflow);
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HANDLE_TEST(test_name, test_illegal_instruction);
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HANDLE_TEST(test_name, test_instr_fetch_prohibited);
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HANDLE_TEST(test_name, test_ub);
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HANDLE_TEST(test_name, test_assert);
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HANDLE_TEST(test_name, test_assert_cache_disabled);
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HANDLE_TEST(test_name, test_assert_cache_write_back_error_can_print_backtrace);
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HANDLE_TEST(test_name, test_assert_cache_write_back_error_can_print_backtrace2);
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HANDLE_TEST(test_name, test_tcb_corrupted);
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#if CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_ESP_COREDUMP_DATA_FORMAT_ELF
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HANDLE_TEST(test_name, test_setup_coredump_summary);
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HANDLE_TEST(test_name, test_coredump_summary);
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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HANDLE_TEST(test_name, test_illegal_access);
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#endif
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#if CONFIG_TEST_MEMPROT
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HANDLE_TEST(test_name, test_iram_reg1_write_violation);
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HANDLE_TEST(test_name, test_iram_reg2_write_violation);
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HANDLE_TEST(test_name, test_iram_reg3_write_violation);
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/* TODO: IDF-6820: ESP32-S2 -> Fix incorrect panic reason: Unhandled debug exception */
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HANDLE_TEST(test_name, test_iram_reg4_write_violation);
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/* TODO: IDF-6820: ESP32-S2-> Fix multiple panic reasons in different runs */
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HANDLE_TEST(test_name, test_dram_reg1_execute_violation);
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HANDLE_TEST(test_name, test_dram_reg2_execute_violation);
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#if CONFIG_SOC_RTC_FAST_MEM_SUPPORTED
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HANDLE_TEST(test_name, test_rtc_fast_reg1_execute_violation);
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HANDLE_TEST(test_name, test_rtc_fast_reg2_execute_violation);
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/* TODO: IDF-6820: ESP32-S2-> Fix multiple panic reasons in different runs */
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HANDLE_TEST(test_name, test_rtc_fast_reg3_execute_violation);
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#endif
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#if SOC_DCACHE_SUPPORTED
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HANDLE_TEST(test_name, test_dcache_read_violation);
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/* TODO: IDF-6820: ESP32-S2-> Fix multiple panic reasons in different runs */
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HANDLE_TEST(test_name, test_dcache_write_violation);
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#endif
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#if CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED
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HANDLE_TEST(test_name, test_rtc_slow_reg1_execute_violation);
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HANDLE_TEST(test_name, test_rtc_slow_reg2_execute_violation);
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#endif
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#if CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT
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HANDLE_TEST(test_name, test_irom_reg_write_violation);
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HANDLE_TEST(test_name, test_drom_reg_write_violation);
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HANDLE_TEST(test_name, test_drom_reg_execute_violation);
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#endif
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#ifdef CONFIG_SOC_CPU_HAS_PMA
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HANDLE_TEST(test_name, test_invalid_memory_region_write_violation);
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HANDLE_TEST(test_name, test_invalid_memory_region_execute_violation);
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#endif
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#endif
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die("Unknown test name");
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}
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