harshal.patil a8f509f481 fix(esp_hw_support): Fix incorrect PMA configuration for ESP32-P4 ... - As the PMA entry that made some memory regions cacheable was assigned the highest priority, some intermediate inaccessible memory regions bypassed protection. - Added tests for the same - Verified that even after changing the priority of the PMA entry, a write operation at SOC_IRAM_LOW + 0x40 (a random RAM cached address) still needs the same number (29) of CPU cycles.		2024-06-10 11:55:58 +05:30
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test_memprot.h	fix(esp_hw_support): Fix incorrect PMA configuration for ESP32-P4	2024-06-10 11:55:58 +05:30
test_panic.h	ci(panic): extend extram_stack tests	2024-05-27 14:51:30 +02:00