alex/esp-idf
alex/esp-idf
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38,770 Commits 20 Branches 148 Tags 384 MiB
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163 Commits

Author SHA1 Message Date
Song Ruo Jing
335d39b869 feat(clk): Add basic clock support for esp32c61 
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
- Remove FPGA build
 2024-07-31 22:41:22 +08:00
Song Ruo Jing
3aa27ae960 refactor(regi2c): add LL function to control analog i2c master clock 2024-07-24 12:26:59 +08:00
Song Ruo Jing
40f3bc2e57 feat(clk): Add basic clock support for esp32c5 mp 
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
- Remove FPGA build
 2024-06-26 14:26:34 +08:00
Wu Zheng Hui
2d36e81ccd Merge branch 'fix/remove_esp32c6_h2_solved_todos' into 'master' 
change(esp_hw_support): remove esp32c6 & esp32h2 solved todos

Closes IDF-5781 and IDF-6254

See merge request espressif/esp-idf!31401
 2024-06-24 13:35:04 +08:00
wuzhenghui
1679b509be
feat(esp_hw_support): support DCDC always on 2024-06-21 16:55:49 +08:00
Xiao Xufeng
5b71b949be fix(startup): move rtc initialization before MSPI timing tuning to improve stability 2024-06-18 01:16:24 +08:00
Song Ruo Jing
ac6101bf4e feat(clk): support ESP32C5 XTAL 40M/48M selection 2024-06-11 17:42:43 +08:00
wuzhenghui
083ef29dcd
change(esp_hw_support): remove esp32c6 & esp32h2 solved todos 2024-06-11 10:20:23 +08:00
wuzhenghui
cca222948a
fix(esp_driver_gpio): manage lp_io module clock by driver 
Closes https://github.com/espressif/esp-idf/issues/13683
 2024-06-05 17:56:37 +08:00
Michael (XIAO Xufeng)
438971c108 Merge branch 'feat/kconfig_h2_v1.0_dev' into 'master' 
esp32h2: add development support option for v1.0 chips

See merge request espressif/esp-idf!30534
 2024-05-21 17:20:56 +08:00
Hong Shu Qing
1a6060fa3a Merge branch 'feature/esp32c6_pu8m_in_sleep_support' into 'master' 
feat(sleep): support 8m force pu in sleep for esp32c6 & esp32h2

See merge request espressif/esp-idf!30532
 2024-05-17 11:34:47 +08:00
chaijie@espressif.com
36bbb64992 feat(sleep): support 8m force pu in sleep for esp32c6/esp32h2 2024-05-16 21:15:05 +08:00
Michael (XIAO Xufeng)
7bff9f9d28 feat(esp32h2): add development support option for v1.0 chips 2024-05-16 02:23:52 +08:00
Linda
52cfd1bf24 docs: fix clock sources for esp32c6 2024-05-07 17:35:39 +08:00
Jiang Jiang Jian
9081d54aa7 Merge branch 'fix/fix_pmu_power_domain_initialize_order' into 'master' 
fix(esp_hw_support): fix pmu power domain initialize order

See merge request espressif/esp-idf!30095
 2024-04-10 17:23:47 +08:00
morris
e8b6d2280d change(gptimer): use private unsafe RCC LL functions in bootloader 2024-04-08 17:48:20 +08:00
wuzhenghui
24244f04f2
fix(esp_hw_support): fix pmu power domain initialize order 2024-04-08 15:47:59 +08:00
Laukik Hase
48503dd39f
fix(esp_hw_support): Fix the flash I/DROM region PMP protection 2024-04-02 18:41:07 +05:30
Li Shuai
262be04b21 change(esp_hw_support): modify system and modem clock to support modem domain power down 2024-03-29 16:13:52 +08:00
wuzhenghui
194c38479e
refactor(esp_hw_support): split pd_top clock retention initialization by target 2024-03-28 19:18:24 +08:00
Omar Chebib
a79c6f7f67 fix(esp_hw_support): clear reserved interrupts that are not applicable for each target 2024-03-27 16:21:25 +08:00
Wu Zheng Hui
5a682c3bbb Merge branch 'feature/optimize_chips_active_power' into 'master' 
feat(system): Optimize the power consumption of esp32h2 and esp32c6 in the active state

Closes IDF-5658

See merge request espressif/esp-idf!27798
 2024-03-14 12:08:33 +08:00
Jiang Jiang Jian
6a879bf2d2 Merge branch 'bugfix/fix_maximum_value_of_config_rtc_clk_cal_cycles_bug' into 'master' 
ESP All Chip: fixed the maximum value of config RTC_CLK_CAL_SYCLES bug

See merge request espressif/esp-idf!29423
 2024-03-14 10:44:17 +08:00
wuzhenghui
129bfce02e feat(esp_hw_support): support esp32p4 pll start/stop event callback 2024-03-10 10:51:28 +08:00
wuzhenghui
856f043331 feat(esp_hw_support): add esp32p4 pmu initial support 2024-03-10 10:51:28 +08:00
wuzhenghui
f5707c6ab8
feat(system): gate the REF_TICK clock by default for esp32c6 and esp32h2 2024-03-07 19:26:38 +08:00
Omar Chebib
eeb5e2f080 Merge branch 'refactor/cpu_interrupt_table' into 'master' 
refactor(Core System/Interrupts): changed reserved interrupt functions to be now defined per SoC

Closes IDF-5728

See merge request espressif/esp-idf!29020
 2024-03-06 11:26:17 +08:00
hongshuqing
d78805670a fix: fix_maximum_value_of_config_rtc_clk_cal_cycle_bug 2024-03-05 19:33:30 +08:00
Omar Chebib
c1849df791 refactor(esp_hw_support): changed reserved interrupt functions to be now defined per SoC 2024-02-28 15:21:10 +08:00
Laukik Hase
366e4ee944
refactor(esp_hw_support): Remove redundant PMP entry for ROM region 
- The ROM text and data sections share the address range
    (see SOC_I/DROM_MASK_LOW - SOC_I/DROM_MASK_HIGH).
  - Initially, we had two PMP entries for this address range - one marking the
    region as RX and the other as R.
  - However, the latter entry is redundant as the former locks the PMP settings.
  - We can divide the ROM region into text and data sections later when we
    define boundaries marking these regions from the ROM.
 2024-02-28 10:54:38 +05:30
Laukik Hase
ff839be31d
fix(esp_hw_support): Fix the I/DCACHE region PMP protection 2024-02-28 10:54:37 +05:30
Song Ruo Jing
dce27c3b09 change(clk_tree): add LP_DYN_FAST_CLK to soc_module_clk_t 2024-02-07 14:37:48 +08:00
wuzhenghui
0c2f811ca8
feat(esp_hw_support): support gdma register context sleep retention 2024-02-02 11:21:40 +08:00
Michael (XIAO Xufeng)
6dbb3059f9 Merge branch 'h2_auto_dbias_master_hsq' into 'master' 
ESP32H2: Active & sleep dbias get from efuse to fix the voltage

See merge request espressif/esp-idf!27483
 2024-01-29 10:16:15 +08:00
Song Ruo Jing
cf93777077 refactor(rtc): move soc/rtc.h from soc to esp_hw_support component 
Deprecated rtc_xtal_freq_t, replaced with soc_xtal_freq_t defined in
clk_tree_defs.h in soc component.
 2024-01-25 19:15:33 +08:00
hongshuqing
0b79d9bf4c feat(pmu): set fix voltage to different mode for esp32h2 
h2 remove include
 2024-01-24 13:11:41 +08:00
Mahavir Jain
e3d4b901f9 Merge branch 'bugfix/compilation_failed_in_bootloader_with_sb_fe_verbose' into 'master' 
fix(bootloader): Fix compilation issue in bootloader build during verbose+sb+fe

Closes IDF-6373

See merge request espressif/esp-idf!26339
 2024-01-23 13:29:02 +08:00
Mahavir Jain
9ecd2fd7e3 fix(soc): change debug addr range to CPU subsystem range 
For C6/H2/P4/C5, there is no SoC specific debug range. Instead the same
address range is part of CPU Subsystem range which contains debug mode
specific code and interrupt config registers (CLINT, PLIC etc.).

For now the PMP entry is provided with RWX permission for both machine
and user mode but we can save this entry and allow the access to only
machine mode for this range.

For P4/C5 case, this PMP entry can have RW permission as the debug mode
specific code is not present in this memory range.
 2024-01-22 13:34:32 +08:00
nilesh.kale
59c5b5fe6b fix(bootloader): Fix compilation issue in bootloader build during verbose+sb+fe 2024-01-18 12:15:15 +05:30
Cao Sen Miao
6768805d20 fix(uart,usj...): Fix wrong serial number that has been parsed to rom functions, 
Closes https://github.com/espressif/esp-idf/issues/12958
 2024-01-18 10:51:51 +08:00
Lou Tian Hao
b74cc4637b Merge branch 'feature/support_hw_trigger_regdma_when_pu_top' into 'master' 
fix(pm):  trigger regdma retention by PMU when TOP is not power down on esp32H2

Closes PM-47 and PM-65

See merge request espressif/esp-idf!28046
 2024-01-08 10:44:06 +08:00
Lou Tianhao
aed3127d19 feat(pm): support PMU trigger regdma when PU TOP 2024-01-05 16:17:32 +08:00
Xiao Xufeng
c204f418ef fix(rtc): fixed bbpll not calibrated from bootloader issue 2024-01-04 03:23:20 +08:00
chaijie@espressif.com
8775b99d93 fix(bbpll): fix bbpll calibration may stop early bug(ESP32C2/S3/C6/H2) 2024-01-04 03:23:20 +08:00
Song Ruo Jing
7f2b85b82b feat(clk): add basic clock support for esp32p4 
- Support CPU frequency 360MHz
- Support SOC ROOT clock source switch
- Support LP SLOW clock source switch
- Support clock calibration
 2023-12-29 00:37:26 +08:00
wuzhenghui
7de2728733 fix(esp_hw_support/sleep): wait flash ready after non-pd_top lightsleep for esp32c6 2023-12-14 08:57:06 +00:00
Marius Vikhammer
ac3915f092 docs(esp32p4): update misc docs for esp32p4 2023-12-09 09:09:55 +08:00
wuzhenghui
e1d24ebd7f fix(esp_hw_support/sleep): fix rtc_time_us_to_slowclk div zero in deepsleep process 
Closes https://github.com/espressif/esp-idf/issues/12695
 2023-12-07 07:50:32 +00:00
Jakob Hasse
637d4c4381 fix(esp_hw_support): Removed unused include directories from cmake 
* Closes https://github.com/espressif/esp-idf/issues/12700
 2023-12-01 11:33:12 +08:00
Li Shuai
fa489d3c20 change(Power Management): the xpd_xtal32k value depends on system slow clock source config option when pmu initialize 2023-10-24 17:11:53 +08:00