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https://github.com/espressif/esp-idf.git
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feat(esp_hw_support): support esp32p4 pll start/stop event callback
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1e17cecd24
commit
129bfce02e
@ -32,8 +32,8 @@ typedef enum {
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SLEEP_EVENT_HW_FLASH_BBPLL_EN_START, // Beginning of rtc_clk_bbpll_enable when using FLASH_PLL
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SLEEP_EVENT_HW_FLASH_BBPLL_EN_STOP, // End of rtc_clk_bbpll_enable when using FLASH_PLL
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#endif
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SLEEP_EVENT_HW_BBPLL_EN_START, // Beginning of rtc_clk_bbpll_enable
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SLEEP_EVENT_HW_BBPLL_EN_STOP, // End of rtc_clk_bbpll_enable
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SLEEP_EVENT_HW_PLL_EN_START, // Beginning of rtc_clk_pll_enable
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SLEEP_EVENT_HW_PLL_EN_STOP, // End of rtc_clk_pll_enable
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SLEEP_EVENT_CB_INDEX_NUM,
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} esp_sleep_event_cb_index_t;
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@ -278,7 +278,7 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
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return true;
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}
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__attribute__((weak)) void rtc_clk_set_cpu_switch_to_bbpll(int event_id)
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__attribute__((weak)) void rtc_clk_set_cpu_switch_to_pll(int event_id)
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{
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}
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@ -295,12 +295,12 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
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} else if ((config->source == SOC_CPU_CLK_SRC_PLL_F160M) || (config->source == SOC_CPU_CLK_SRC_PLL_F240M)) {
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if ((old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL_F160M) && (old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL_F240M)) {
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// PLL_F160M and PLL_F240M both derived from S(BB)PLL (480MHz)
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rtc_clk_set_cpu_switch_to_bbpll(SLEEP_EVENT_HW_BBPLL_EN_START);
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rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_START);
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rtc_clk_bbpll_enable();
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rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), CLK_LL_PLL_480M_FREQ_MHZ);
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}
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rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
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rtc_clk_set_cpu_switch_to_bbpll(SLEEP_EVENT_HW_BBPLL_EN_STOP);
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rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_STOP);
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} else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
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rtc_clk_cpu_freq_to_8m();
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if (((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F160M) || (old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F240M)) && !s_bbpll_digi_consumers_ref_count) {
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@ -254,7 +254,7 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
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return true;
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}
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__attribute__((weak)) void rtc_clk_set_cpu_switch_to_bbpll(int event_id)
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__attribute__((weak)) void rtc_clk_set_cpu_switch_to_pll(int event_id)
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{
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}
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@ -269,12 +269,12 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
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}
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} else if (config->source == SOC_CPU_CLK_SRC_PLL) {
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if (old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL) {
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rtc_clk_set_cpu_switch_to_bbpll(SLEEP_EVENT_HW_BBPLL_EN_START);
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rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_START);
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rtc_clk_bbpll_enable();
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rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), config->source_freq_mhz);
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}
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rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
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rtc_clk_set_cpu_switch_to_bbpll(SLEEP_EVENT_HW_BBPLL_EN_STOP);
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rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_STOP);
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} else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
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rtc_clk_cpu_freq_to_8m();
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if ((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL) && !s_bbpll_digi_consumers_ref_count) {
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@ -298,7 +298,7 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
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return true;
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}
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__attribute__((weak)) void rtc_clk_set_cpu_switch_to_bbpll(int event_id)
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__attribute__((weak)) void rtc_clk_set_cpu_switch_to_pll(int event_id)
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{
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}
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@ -313,12 +313,12 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
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}
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} else if (config->source == SOC_CPU_CLK_SRC_PLL) {
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if (old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL && old_cpu_clk_src != SOC_CPU_CLK_SRC_FLASH_PLL) {
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rtc_clk_set_cpu_switch_to_bbpll(SLEEP_EVENT_HW_BBPLL_EN_START);
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rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_START);
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rtc_clk_bbpll_enable();
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rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), config->source_freq_mhz);
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}
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rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
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rtc_clk_set_cpu_switch_to_bbpll(SLEEP_EVENT_HW_BBPLL_EN_STOP);
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rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_STOP);
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} else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
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rtc_clk_cpu_freq_to_8m();
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if ((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL || old_cpu_clk_src == SOC_CPU_CLK_SRC_FLASH_PLL) &&
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@ -329,12 +329,12 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
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if (old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL && old_cpu_clk_src != SOC_CPU_CLK_SRC_FLASH_PLL) {
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// On ESP32H2, FLASH_PLL (64MHz) is directly derived from the BBPLL (96MHz)
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// Therefore, enabling and configuration are applied to BBPLL.
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rtc_clk_set_cpu_switch_to_bbpll(SLEEP_EVENT_HW_FLASH_BBPLL_EN_START);
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rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_FLASH_BBPLL_EN_START);
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rtc_clk_bbpll_enable();
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rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), CLK_LL_PLL_96M_FREQ_MHZ);
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}
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rtc_clk_cpu_freq_to_flash_pll(config->freq_mhz, config->div);
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rtc_clk_set_cpu_switch_to_bbpll(SLEEP_EVENT_HW_FLASH_BBPLL_EN_STOP);
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rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_FLASH_BBPLL_EN_STOP);
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}
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}
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@ -300,6 +300,10 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
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return true;
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}
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__attribute__((weak)) void rtc_clk_set_cpu_switch_to_pll(int event_id)
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{
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}
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void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
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{
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soc_cpu_clk_src_t old_cpu_clk_src = clk_ll_cpu_get_src();
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@ -310,6 +314,7 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
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}
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} else if (config->source == SOC_CPU_CLK_SRC_CPLL) {
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if (old_cpu_clk_src != SOC_CPU_CLK_SRC_CPLL) {
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rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_START);
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rtc_clk_cpll_enable();
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}
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if (config->source_freq_mhz != s_cur_cpll_freq) {
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@ -319,6 +324,7 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
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rtc_clk_cpll_configure(xtal_freq_mhz, config->source_freq_mhz);
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}
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rtc_clk_cpu_freq_to_cpll_mhz(config->freq_mhz, (hal_utils_clk_div_t *)&config->div);
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rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_STOP);
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} else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
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rtc_clk_cpu_freq_to_8m();
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if (old_cpu_clk_src == SOC_CPU_CLK_SRC_CPLL) {
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