Commit Graph

57 Commits

Author SHA1 Message Date
morris
e30cd361a8 global: rename esp32s2beta to esp32s2 2020-01-22 12:14:38 +08:00
Angus Gratton
c7738f24fc Merge branch 'bugfix/ledc_driver_enums' into 'master'
driver: Avoid possible accidental mismatch between ledc_clk_src_t & ledc_clk_cfg_t enum

See merge request espressif/esp-idf!7021
2020-01-10 15:34:43 +08:00
Darian Leung
a049e02d96 can: Refactor CAN to use HAL and LowLevel layers
The following commit refactors the CAN driver such that
it is split into HAL and Lowlevel layers. The following
changes have also been made:

- Added bit field members to can_message_t as alternative
  to message flags. Updated examples and docs accordingly
- Register field names and fields of can_dev_t updated
2020-01-09 16:13:51 +08:00
Ivan Grokhotkov
e4d45608d3 soc: add ledc_caps.h, replace target-based ifdefs with caps-based 2019-12-28 20:33:21 +00:00
kewal shah
eec8212237 add simplified API to set UART threshold values for RX FIFO full and TX FIFO empty 2019-12-16 20:26:04 +00:00
Angus Gratton
435dd546cc driver: Avoid possible accidental mismatch between ledc_clk_src_t & ledc_clk_cfg_t enum
ledc_types.h includes two similar enums, ledc_clk_src_t & ledc_clk_cfg_t. Latter was added in
ESP-IDF v4.0.

The two enums do different things but there are two similar names: LEDC_REF_TICK / LEDC_USE_REF_TICK
and LEDC_APB_CLK / LEDC_USE_APB_CLK.

Because C will accept any enum or integer value for an enum argument, there's no easy way to check
the correct enum is passed without using static analysis.

To avoid accidental errors, make the numeric values for the two similarly named enums the same.,

Noticed when looking into https://github.com/espressif/esp-idf/issues/4476
2019-12-16 19:43:11 +11:00
Michael (XIAO Xufeng)
0ec08ca21b sdio_slave: support HAL layer 2019-12-13 18:33:15 +08:00
houwenxiang
aac935ec81 bugfix(i2c): fix I2C driver breaking change issue.
1. Fixed I2C driver breaking change issue.
    2. Add I2C UT test case.
2019-12-04 15:51:36 +08:00
Wang Jia Lin
1ffcb54444 Merge branch 'bugfix/fix_esp32-s2_rtc_io_issue' into 'master'
bugfix(gpio): fix esp32 s2 rtc io issue and gpio testcase issues

See merge request espressif/esp-idf!6832
2019-12-03 11:17:41 +08:00
Renz Christian Bagaporo
e6ad330018 ble_mesh_wifi_coexist example: Disable Wi-Fi RX IRAM optimisation
Otherwise IRAM usage is too high in this example.
2019-11-28 09:20:00 +08:00
Fu Zhi Bo
3a468a1ffd Refactor the touch sensor driver 2019-11-27 20:08:44 +08:00
xiongyu
af4c455417 bugfix(gpio):fix esp32 s2 rtc io issue
* Modify the function implementation of ESP32-S2 RTC GPIO
  On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register.
  On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
* Add ESP32-S2 support of unit test
* Modify the pull-up test of unit test
* Modify the interrupt test of unit test
* Modify input and output mode test of unit test
2019-11-27 17:18:20 +08:00
Angus Gratton
91b7a7beaf Merge branch 'bugfix/timer_intr_status_get' into 'master'
bugfix(timer): fix get intr status function

See merge request espressif/esp-idf!6807
2019-11-27 09:13:16 +08:00
chenjianqiang
bcfe684951 bugfix(timer): add a macro to control making the XTAL related functions 2019-11-26 12:39:46 +00:00
chenjianqiang
856d9f7d89 bugfix(timer): recover get raw interrupt status function 2019-11-26 12:39:46 +00:00
houwenxiang
f27ae9b0e2 feature: Add uart hal support. 2019-11-26 20:01:50 +08:00
Angus Gratton
f2a1a6105a Merge branch 'feat/mcpwm_hal'
Manual merge of !6626
2019-11-25 17:18:48 +11:00
Angus Gratton
6dd36fd571 Merge branch 'refactor/hal_gpio_driver'
Manual merge of !5597
2019-11-25 10:49:40 +11:00
Angus Gratton
f34edba8f3 Merge branch 'feature/adc_driver_hal_support'
Manual merge of !6044
2019-11-25 10:22:06 +11:00
michael
538540ce21 mcpwm: add HAL layer support
Also improved the unit tests a bit.
2019-11-25 00:36:30 +08:00
xiongyu
a3b79e9202 refactor(gpio): add hal gpio driver 2019-11-22 17:24:53 +08:00
fuzhibo
f49b192a5e refactor the adc driver 2019-11-22 15:42:16 +08:00
Mahavir Jain
25c0752682 i2s: fix regression in retrieval of chip revision causing apll test to fail 2019-11-22 11:46:38 +05:30
fuzhibo
03ac1aaafd dac: refactor driver add hal 2019-11-22 11:44:46 +08:00
houwenxiang
28286183d1 feature(I2C): Add i2c hal support. 2019-11-21 20:34:07 +08:00
chenjianqiang
857dec108d feat(ledc): refactor ledc driver
1. add hal and low-level layer for ledc driver
2. support esp32s2beta ledc
2019-11-21 16:25:22 +08:00
chenjianqiang
9f9da9ec96 feat(timer): refator timer group driver
1. add hal and low-level layer for timer group
2. add callback functions to handle interrupt
3. add timer deinit function
4. add timer spinlock take function
2019-11-21 14:14:19 +08:00
xiongyu
e62b831867 refactor(sigmadelta): add hal sigmadelta driver 2019-11-21 11:53:07 +08:00
fuzhibo
0c2bf7c8bc rtcio: add hal for driver 2019-11-21 10:40:49 +08:00
Angus Gratton
b30b0e59fa Merge branch 'feature/add_rmt_hal' into 'master'
rmt: add hal layer and new examples

Closes IDF-841, IDF-844, and IDF-857

See merge request espressif/esp-idf!5649
2019-11-21 09:53:54 +08:00
morris
8fd8695ea1 rmt: add HAL layer 2019-11-20 10:54:21 +08:00
xiongyu
8c76a3c10d refactor(i2s): add hal i2s driver 2019-11-19 22:19:19 +08:00
xiongyu
b1a72866ca refactor(pcnt): add hal pcnt driver 2019-11-18 14:35:46 +08:00
Angus Gratton
8675a818f9 Merge branch 'master' into feature/esp32s2beta_merge 2019-10-22 13:51:49 +11:00
Michael (XIAO Xufeng)
571864e8ae esp_flash: fix set qe bit and write command issues
There used to be dummy phase before out phase in common command
transactions. This corrupts the data.

The code before never actually operate (clear) the QE bit, once it finds
the QE bit is set. It's hard to check whether the QE set/disable
functions work well.

This commit:

1. Cancel the dummy phase

2. Set and clear the QE bit according to chip settings, allowing tests
   for QE bits. However for some chips (Winbond for example), it's not
   forced to clear the QE bit if not able to.

3. Also refactor to allow chip_generic and other chips to share the same
   code to read and write qe bit; let common command and read command share
   configure_host_io_mode.

4. Rename read mode to io mode since maybe we will write data with quad
   mode one day.
2019-10-14 17:25:58 +08:00
Angus Gratton
adfc06a530 Merge branch 'master' into feature/esp32s2beta_merge 2019-09-20 10:28:37 +10:00
Angus Gratton
438d513a95 Merge branch 'master' into feature/esp32s2beta_merge 2019-09-16 16:18:48 +10:00
Michael (XIAO Xufeng)
511820820e esp_flash: fix the coredump issue
During coredump, dangerous-area-checking should be disabled, and cache
disabling should be replaced by a safer version.

Dangerous-area-checking used to be in the HAL, but it seems to be more
fit to os functions. So it's moved to os functions. Interfaces are
provided to switch between os functions during coredump.
2019-09-14 17:01:36 +08:00
Roland Dobai
612db28b6f Fix error code collision and CI check 2019-08-29 08:14:08 +00:00
Angus Gratton
6990a7cd54 Merge branch 'master' into feature/esp32s2beta_update 2019-08-19 15:03:43 +10:00
Angus Gratton
74c2eb3aff Merge branch 'fix/esp_flash_set_get_wp' into 'master'
esp_flash: fix the set/get write protection functions

See merge request espressif/esp-idf!5682
2019-08-16 06:14:48 +08:00
Michael (XIAO Xufeng)
d850a0bd1c esp_attr: add flag_attr to support enums used as flags 2019-08-09 13:46:32 +08:00
Michael (XIAO Xufeng)
feea477023 timer_group: add LL functions for WDT 2019-08-09 13:46:30 +08:00
Michael (XIAO Xufeng)
c02981a99b timer_group: support interrupt LL and some utility functions in ISR 2019-08-09 13:46:30 +08:00
chenjianqiang
a97fe5615f feat(timer): refator timer group driver (partly pick) 2019-08-09 13:46:29 +08:00
Michael (XIAO Xufeng)
e947522f38 esp_flash: improve the comments a bit 2019-08-08 23:18:01 +08:00
Angus Gratton
24d26fccde Merge branch 'master' into feature/esp32s2beta_update 2019-08-08 13:44:24 +10:00
Michael (XIAO Xufeng)
d6bd24ca67 esp_flash: add initialization interface for SPI devices 2019-06-27 13:27:27 +08:00
Michael (XIAO Xufeng)
17378fd4c2 spi: support new chip esp32s2beta 2019-06-23 12:17:27 +08:00
Michael (XIAO Xufeng)
9b13a04abf spi: multichip support
move hardcoded numbers, etc. into soc files.
create headers for shared types which needs to be documented.

(MINOR CHANGE)
2019-06-22 19:08:47 +08:00