alex/esp-idf
alex/esp-idf
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10,980 Commits 20 Branches 148 Tags 384 MiB
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Commit Graph

222 Commits

Author SHA1 Message Date
Angus Gratton
91b7a7beaf Merge branch 'bugfix/timer_intr_status_get' into 'master' 
bugfix(timer): fix get intr status function

See merge request espressif/esp-idf!6807
 2019-11-27 09:13:16 +08:00
Angus Gratton
64c8b640a1 Merge branch 'feature/log_component_noos' into 'master' 
log: make compatible with non-OS builds

See merge request espressif/esp-idf!6787
 2019-11-27 08:34:22 +08:00
chenjianqiang
bcfe684951 bugfix(timer): add a macro to control making the XTAL related functions 2019-11-26 12:39:46 +00:00
chenjianqiang
856d9f7d89 bugfix(timer): recover get raw interrupt status function 2019-11-26 12:39:46 +00:00
houwenxiang
f27ae9b0e2 feature: Add uart hal support. 2019-11-26 20:01:50 +08:00
Angus Gratton
f2a1a6105a Merge branch 'feat/mcpwm_hal' 
Manual merge of !6626
 2019-11-25 17:18:48 +11:00
Angus Gratton
6dd36fd571 Merge branch 'refactor/hal_gpio_driver' 
Manual merge of !5597
 2019-11-25 10:49:40 +11:00
Angus Gratton
f34edba8f3 Merge branch 'feature/adc_driver_hal_support' 
Manual merge of !6044
 2019-11-25 10:22:06 +11:00
michael
538540ce21 mcpwm: add HAL layer support 
Also improved the unit tests a bit.
 2019-11-25 00:36:30 +08:00
xiongyu
a3b79e9202 refactor(gpio): add hal gpio driver 2019-11-22 17:24:53 +08:00
fuzhibo
f49b192a5e refactor the adc driver 2019-11-22 15:42:16 +08:00
Mahavir Jain
25c0752682 i2s: fix regression in retrieval of chip revision causing apll test to fail 2019-11-22 11:46:38 +05:30
fuzhibo
03ac1aaafd dac: refactor driver add hal 2019-11-22 11:44:46 +08:00
Ivan Grokhotkov
951ed739f7 soc/cpu: add non-xtensa-specific replacement of xthal_get_ccount 2019-11-21 19:22:35 +01:00
houwenxiang
28286183d1 feature(I2C): Add i2c hal support. 2019-11-21 20:34:07 +08:00
chenjianqiang
857dec108d feat(ledc): refactor ledc driver 
1. add hal and low-level layer for ledc driver
2. support esp32s2beta ledc
 2019-11-21 16:25:22 +08:00
chenjianqiang
9f9da9ec96 feat(timer): refator timer group driver 
1. add hal and low-level layer for timer group
2. add callback functions to handle interrupt
3. add timer deinit function
4. add timer spinlock take function
 2019-11-21 14:14:19 +08:00
xiongyu
e62b831867 refactor(sigmadelta): add hal sigmadelta driver 2019-11-21 11:53:07 +08:00
fuzhibo
0c2bf7c8bc rtcio: add hal for driver 2019-11-21 10:40:49 +08:00
Angus Gratton
b30b0e59fa Merge branch 'feature/add_rmt_hal' into 'master' 
rmt: add hal layer and new examples

Closes IDF-841, IDF-844, and IDF-857

See merge request espressif/esp-idf!5649
 2019-11-21 09:53:54 +08:00
morris
8fd8695ea1 rmt: add HAL layer 2019-11-20 10:54:21 +08:00
xiongyu
8c76a3c10d refactor(i2s): add hal i2s driver 2019-11-19 22:19:19 +08:00
xiongyu
b1a72866ca refactor(pcnt): add hal pcnt driver 2019-11-18 14:35:46 +08:00
Angus Gratton
8675a818f9 Merge branch 'master' into feature/esp32s2beta_merge 2019-10-22 13:51:49 +11:00
Ivan Grokhotkov
c7d8ef52ca Merge branch 'fix/esp_flash_no_qe' into 'master' 
esp_flash: fix the QE write issue in high freq, and support UT for external chips

Closes IDF-888

See merge request espressif/esp-idf!5736
 2019-10-20 13:59:30 +08:00
Angus Gratton
ae21d669b9 Merge branch 'master' into feature/esp32s2beta_merge 2019-10-17 18:22:08 +11:00
Darian
820fd6447d can: Add support for lower bit rates 
This commit adds support for lower bit rates in the CAN Driver for
ESP32 Rev 2 or later chips.
 2019-10-17 12:33:17 +08:00
Angus Gratton
496ede9bcd Merge branch 'master' into feature/esp32s2beta_merge 2019-10-15 14:59:27 +11:00
Michael (XIAO Xufeng)
571864e8ae esp_flash: fix set qe bit and write command issues 
There used to be dummy phase before out phase in common command
transactions. This corrupts the data.

The code before never actually operate (clear) the QE bit, once it finds
the QE bit is set. It's hard to check whether the QE set/disable
functions work well.

This commit:

1. Cancel the dummy phase

2. Set and clear the QE bit according to chip settings, allowing tests
   for QE bits. However for some chips (Winbond for example), it's not
   forced to clear the QE bit if not able to.

3. Also refactor to allow chip_generic and other chips to share the same
   code to read and write qe bit; let common command and read command share
   configure_host_io_mode.

4. Rename read mode to io mode since maybe we will write data with quad
   mode one day.
 2019-10-14 17:25:58 +08:00
suda-morris
13c128fd31 Ethernet: optimize and bugfix 
1. simplify deallocate in esp_eth_mac_new_esp32, esp_eth_mac_new_dm9051
2. remove blocking operation in os timer callback
3. check buffer size in ethernet receive function
 2019-10-11 12:15:17 +08:00
Angus Gratton
adfc06a530 Merge branch 'master' into feature/esp32s2beta_merge 2019-09-20 10:28:37 +10:00
Jack
95ec36afd4 dport: remove clock_en and reset bitname which is not suitable 2019-09-13 09:44:07 +10:00
Angus Gratton
33a186f630 soc: Remove deprecated LEDC struct register names (bit_num, div_num) 
Deprecated since ESP-IDF V3.0
 2019-09-13 09:44:07 +10:00
Angus Gratton
6195c69701 soc: remove deprecated io_mux PIN_PULLxxx_yyy macros 
Deprecated before ESP-IDF V1.0!
 2019-09-13 09:44:07 +10:00
Angus Gratton
11c1da5276 soc/pm: Remove deprecated use of rtc_cpu_freq_t enum 
Removes deprecated ways of setting/getting CPU freq, light sleep freqs.

Deprecated since ESP-IDF V3.2
 2019-09-13 09:44:07 +10:00
Angus Gratton
35147119f1 Merge branch 'feature/support_ut_esp32s2beta' into 'feature/esp32s2beta' 
ci: support build and run UT for esp32s2beta

See merge request espressif/esp-idf!5702
 2019-09-09 08:34:16 +08:00
Li Shuai
bd29202520 1. Fix backtrace is incomplete 
2. Optimization code style
 2019-09-05 18:40:33 +08:00
Michael (XIAO Xufeng)
43135dc348 spi: convenient LL macro 2019-09-04 10:53:25 +10:00
Michael (XIAO Xufeng)
05739798c3 soc: s2beta support 2019-09-04 10:53:25 +10:00
Angus Gratton
6990a7cd54 Merge branch 'master' into feature/esp32s2beta_update 2019-08-19 15:03:43 +10:00
Angus Gratton
367ecc2d60 Merge branch 'refactor/timerg_in_test' into 'master' 
timer_group: refactoring to avoid direct register access in the ISR

See merge request espressif/esp-idf!5656
 2019-08-14 15:32:16 +08:00
suda-morris
f86e82cb63 efuse: update the scheme of getting chip revision 2019-08-13 10:59:02 +08:00
Michael (XIAO Xufeng)
feea477023 timer_group: add LL functions for WDT 2019-08-09 13:46:30 +08:00
Michael (XIAO Xufeng)
c02981a99b timer_group: support interrupt LL and some utility functions in ISR 2019-08-09 13:46:30 +08:00
chenjianqiang
a97fe5615f feat(timer): refator timer group driver (partly pick) 2019-08-09 13:46:29 +08:00
Angus Gratton
04ae56806c Merge branch 'master' into feature/esp32s2beta_update 2019-08-08 15:26:58 +10:00
Angus Gratton
24d26fccde Merge branch 'master' into feature/esp32s2beta_update 2019-08-08 13:44:24 +10:00
kooho
2139ca668d Update I2S driver for esp32s2beta. 2019-08-05 16:05:16 +08:00
Anton Maklakov
afbaf74007 tools: Mass fixing of empty prototypes (for -Wstrict-prototypes) 2019-08-01 16:28:56 +07:00
chenjianqiang
91ae40e2ff uart: multichip support 2019-07-18 15:57:00 +08:00