20 Commits

Author	SHA1	Message	Date
wanlei	217e36bec0	spi: fix spi support on h4 after diver/cmakelist refactored	2023-02-15 12:12:22 +08:00
wanlei	5300bd3b2f	spi: support H2 spi master, slave, slave_hd driver	2023-02-08 11:38:45 +08:00
Armando	d233f3535d	flash_mmap: migrate to use esp_mmap driver	2023-02-07 20:23:52 +08:00
Armando	d6844051fc	esp_mm: new virtual memory mapping apis via mmu	2023-02-07 20:23:52 +08:00
wanlei	6ec9802eb7	spi_master: fix clock source RC_FAST usage	2023-02-06 12:41:17 +08:00
jiangguangming	b0fa18d290	ci: fix typos tag naming of all flash_multi	2023-02-01 08:46:48 +08:00
wanlei	713dc06661	spi: add feature to modify core_id of spi isr regstered	2023-01-30 16:14:02 +08:00
wanlei	184145817c	spi_master: add feature spi periph clk source selectable	2023-01-18 15:40:12 +08:00
Cao Sen Miao	94120b82c2	esp32h2: add build test	2023-01-17 10:29:04 +08:00
wanlei	120d54d700	test: formate test_spi_slave.c	2023-01-04 15:35:04 +08:00
wanlei	45c1dc424f	spi_slave: add spi 'spi_slave_queue_reset_isr' and add test	2023-01-04 15:35:04 +08:00
wanlei	6ae852f8b0	spi_slave: add api 'queue_trans_isr' and add a test case	2023-01-04 15:35:04 +08:00
wanlei	971eaa0c08	spi_slave: fix spi_slave_isr iram_safe and add test case for it	2023-01-04 15:35:04 +08:00
wanlei	dd50bb2d50	test: enable multi-board test of spi for c6	2022-12-07 11:37:48 +08:00
wanlei	5c099a2a49	test: re-enable some test cases of spi for esp32c2	2022-12-07 11:37:48 +08:00
Song Ruo Jing	7466ddfa8c	ci: Make consistence between pytest_*.py and .build-test-rules.yml for esp32c6 (i.e. to pass check_test_scripts_build_test_rules.py)	2022-11-28 11:58:30 +08:00
Song Ruo Jing	e13a4ad963	ci: Disable some unit-test-apps for esp32c6 to pass ci build stage	2022-11-28 11:58:30 +08:00
wanlei	3aeedc2ad3	spi: bringup c6 spi master & slave driver support	2022-11-18 15:54:14 +08:00
Armando	a7289587d3	spi_slave: add a test to internal api spi_slave_reset_trans_queue	2022-11-14 16:01:48 +08:00
wanlei	f31ecbb42b	test: move spi related unit-test into pytest app	2022-11-10 16:02:03 +08:00