Commit Graph

25 Commits

Author SHA1 Message Date
Wan Lei
da73e0f8a2 Merge branch 'fix/spi_sct_fix_descripter_oob_when_lager_then_4092' into 'master'
fix(spi_master): fix sct mode descripter oob when data lager then 4092 bytes

See merge request espressif/esp-idf!30545
2024-05-20 11:49:18 +08:00
Alexey Gerenkov
8b93323da6 Merge branch 'upgrade_clang_toolchain' into 'master'
Upgrade clang toolchain version to 'esp-17.0.1_20240419'

See merge request espressif/esp-idf!29811
2024-05-14 21:47:06 +08:00
wanlei
4f424da1ee fix(spi_master): fix sct mode descripter oob when data lager then 4092 bytes 2024-05-13 11:42:29 +08:00
Alexey Gerenkov
3482277bfe fix(build): Fix '-Werror=format=' errors for esp32p4 2024-05-03 16:55:18 +03:00
Alexey Gerenkov
41bfac91d9 fix(build): Fix printf formating errors 2024-05-03 16:55:18 +03:00
wanlei
cb86a3e2a2 feat(spi): Add helper function for alignment reqiured memory allocation 2024-04-24 14:01:09 +08:00
wanlei
c82ea4311e refactor(spi_slave_hd): replace part of dma_ll in hd hal layer 2024-04-24 14:01:09 +08:00
wanlei
67f798b666 refactor(spi_slave): replace dma_ll in slave hal layer (part 2.2) 2024-04-24 14:01:09 +08:00
Armando
d341540a5e change(drivers): other driver changes for cache malloc 2024-04-15 15:34:51 +08:00
morris
f29351b99a refactor(spi): use RCC functions to do DMA reset 2024-03-29 10:53:05 +08:00
Wan Lei
e84c7f00a5 Merge branch 'feat/c6lite_c61_ci_header_tmp_app' into 'master'
feat(esp32c61): ci enable header check (stage 7/8)

See merge request espressif/esp-idf!29775
2024-03-28 11:45:20 +08:00
morris
c0289ee6eb fix(drivers): fix typos found by codespell
codespell components/esp_driver*
2024-03-28 10:01:27 +08:00
wanlei
535afdd7f4 feat(esp32c61): ci enable header check, fix c61 build 2024-03-27 19:39:59 +08:00
wanlei
51ffd40843 feat(spi_master): rebase dma sct mode support, rename APIs, use malloc conf_buffer 2024-03-20 16:06:43 +08:00
wanlei
1e6c61daa6 spi_master: sct mode support set line mode, transaction interval time
support line mode 1-2-4-8 depend on targets.
fix sct mode dma descriptor counter compute issue.
add conf_bits_len setting API to control interval time.
2024-03-20 15:42:03 +08:00
Armando
b303e4b7a6 spi_master: new segmented-configure-transfer mode 2024-03-20 15:42:03 +08:00
wanlei
0cf11e5b87 feat(spi): add esp32c5 spi support 2024-03-07 18:11:48 +08:00
wanlei
45cbcad7cd fix(spi_master): fix P4 clock src divider and 8bit support 2024-01-26 14:51:46 +08:00
wanlei
4a46d70e9a fix(spi_master): Fix p4 spi clock source support other than XTAL 2024-01-17 17:01:23 +08:00
wanlei
2baee4fb0f refactor(spi_master): replace dma_ll in spi hal layer (part 2.1) 2023-12-28 19:58:54 +08:00
wanlei
25c17da4bb fix(spi_slave): correct param check for trans APIs 2023-12-14 12:57:02 +00:00
wanlei
d0023b061f refactor(spi): replace dma_ll related in spi by dma driver (part1) 2023-12-04 16:20:05 +08:00
Marius Vikhammer
52e3f09b32 refactor(spi): moved spi hw sharing func to hw support
Common spi functionality for sharing the SPI bus between modules is moved from esp_driver_spi to
a more fitting location in esp_hw_support (shared HW resource control).

This also allows us to decouple the spi_flash driver from esp_driver_spi, removing
esp_driver_spi and esp_ringbuf from G1 builds.
2023-11-20 12:07:54 +08:00
Armando
714ad573e7 refactor(esp_driver_spi): reformat code with astyle_py 2023-11-09 14:50:05 +08:00
Armando
fca46eac52 refactor(spi): make spi driver as component 2023-11-09 14:50:05 +08:00