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fix(build): Fix printf formating errors
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e86f1e8a7f
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41bfac91d9
@ -591,7 +591,7 @@ static esp_err_t s_spi_slave_hd_setup_priv_trans(spi_host_device_t host, spi_sla
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if (((uint32_t)orig_trans->data) | (byte_len & (alignment - 1))) {
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ESP_RETURN_ON_FALSE(orig_trans->flags & SPI_SLAVE_HD_TRANS_DMA_BUFFER_ALIGN_AUTO, ESP_ERR_INVALID_ARG, TAG, "data buffer addr&len not align to %d, or not dma_capable", alignment);
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byte_len = (byte_len + alignment - 1) & (~(alignment - 1)); // up align to alignment
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ESP_LOGD(TAG, "Re-allocate %s buffer of len %ld for DMA", (chan == SPI_SLAVE_CHAN_TX) ? "TX" : "RX", byte_len);
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ESP_LOGD(TAG, "Re-allocate %s buffer of len %d for DMA", (chan == SPI_SLAVE_CHAN_TX) ? "TX" : "RX", byte_len);
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priv_trans->aligned_buffer = heap_caps_aligned_alloc(64, byte_len, MALLOC_CAP_DMA);
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if (priv_trans->aligned_buffer == NULL) {
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return ESP_ERR_NO_MEM;
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@ -135,7 +135,7 @@ static bool check_huk_info_validity(const esp_key_mgr_huk_info_t *huk_info)
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{
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uint32_t calc_crc = esp_rom_crc32_le(0, huk_info->info, KEY_MGR_HUK_INFO_SIZE);
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if (calc_crc != huk_info->crc) {
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ESP_LOGE(TAG, "Calculated CRC for HUK %lX does not match with %lX", calc_crc, huk_info->crc);
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ESP_LOGE(TAG, "Calculated CRC for HUK %X does not match with %X", calc_crc, huk_info->crc);
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return false;
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}
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return true;
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@ -145,7 +145,7 @@ static bool check_key_info_validity(const esp_key_mgr_key_info_t *key_info)
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{
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uint32_t calc_crc = esp_rom_crc32_le(0, key_info->info, KEY_MGR_KEY_RECOVERY_INFO_SIZE);
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if (calc_crc != key_info->crc) {
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ESP_LOGE(TAG, "Calculated CRC for Key info %lX does not match with %lX", calc_crc, key_info->crc);
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ESP_LOGE(TAG, "Calculated CRC for Key info %X does not match with %X", calc_crc, key_info->crc);
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return false;
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}
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return true;
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@ -76,7 +76,7 @@ void mipi_dsi_hal_configure_phy_pll(mipi_dsi_hal_context_t *hal, uint32_t phy_cl
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mipi_dsi_hal_phy_write_register(hal, 0x18, 0x80 | (((pll_M - 1) >> 5) & 0x0F));
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// update the real lane bit rate
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hal->lane_bit_rate_mbps = ref_freq_mhz * pll_M / pll_N;
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HAL_LOGD("dsi_hal", "phy pll: ref=%luHz, lane_bit_rate=%luMbps, M=%d, N=%d, hsfreqrange=%d",
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HAL_LOGD("dsi_hal", "phy pll: ref=%uHz, lane_bit_rate=%uMbps, M=%d, N=%d, hsfreqrange=%d",
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phy_clk_src_freq_hz, hal->lane_bit_rate_mbps, pll_M, pll_N, hs_freq_sel);
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}
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