Moved FreeRTOSConfig.h from include/freertos to include/esp_additions/freertos.
Updated FreeRTOS.h file to include FreeRTOSConfig.h without the
freertos/ prefix to match with the upstream file.
Renamed architecture specific FreeRTOSConfig.h files to FreeRTOSConfig_arch.h
Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
components/os: Move ETS_T1_WDT_INUM, ETS_CACHEERR_INUM and ETS_DPORT_INUM to l5 interrupt
components/os: high level interrupt(5)
components/os: hli_api: meta queue: fix out of bounds access, check for overflow
components/os: hli: don't spill registers, instead save them to a separate region
Level 4 interrupt has a chance of preempting a window overflow or underflow exception.
Therefore it is not possible to use standard context save functions,
as the SP on entry to Level 4 interrupt may be invalid (e.g. in WindowUnderflow4).
Instead, mask window overflows and save the entire general purpose register file,
plus some of the special registers.
Then clear WindowStart, allowing the C handler to execute without spilling the old windows.
On exit from the interrupt handler, do everything in reverse.
components/bt: using high level interrupt in lc
components/os: Add DRAM_ATTR to avoid feature `Allow .bss segment placed in external memory`
components/bt: optimize code structure
components/os: Modify the BT assert process to adapt to coredump and HLI
components/os: Disable exception mode after saving special registers
To store some registers first, avoid stuck due to live lock after disabling exception mode
components/os: using dport instead of AHB in BT to fix live lock
components/bt: Fix hli queue send error
components/bt: Fix CI fail
# Conflicts:
# components/bt/CMakeLists.txt
# components/bt/component.mk
# components/bt/controller/bt.c
# components/bt/controller/lib
# components/esp_common/src/int_wdt.c
# components/esp_system/port/soc/esp32/dport_panic_highint_hdl.S
# components/soc/esp32/include/soc/soc.h
Moved the inclusion of esp_compiler.h from FreeRTOS.h to
the app specific FreeRTOSConfig.h where the unlikely()
macro is used. This change is in alignment with the upstream
FreeRTOS.h file.
Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
xSemaphoreAltTake and xSemaphoreAltGive are Espressif defined macros and
are not being used. The respective definitions, xQueueAltGenericReceive
and xQueueAltGenericSend are also not part of current FreeRTOS source
(v10.4.3). Hence, removed xSemaphoreAltTake and xSemaphoreAltGive
definitions to align with upstream code.
Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
systimer was stopped because the option SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN is set by default 1, it blocks counting.
For Unicore should be:
SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN 1
SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN 0
* ##__VA_ARGS__ is replaced by __VA_OPT__(,)
and __VA_ARGS if C++20 is used.
* Affected header files are: esp_log.h,
portmacro.h and esp_check.h
* Closes https://github.com/espressif/esp-idf/pull/6692
portGET_ARGUMENT_COUNT uses a GCC extension ##__VA_ARGS__. It forces
the user to compile the code with GNU extensions enabled instead of ISO
language standard. The suggested change is to replace ##__VA_ARGS__ with
__VA_OPT__(,) __VA_ARGS__ which is supported by the current version of
GCC used in ESP-IDF for both C and C++ ISO standards.
This fix would enable ESP-IDF users to compile their code with ISO C++20
standard in future releases.
Signed-off-by: Jakob Hasse <jakob.hasse@espressif.com>
1. Add conditions based on Kconfig options for functions which are
compiled based on those options.
2. Static allocation is always enabled, move corresponding functions
into the common list.
Since dd849ffc, _rodata_start label has been moved to a different
linker output section from where the TLS templates (.tdata, .tbss)
are located. Since link-time addresses of thread-local variables are
calculated relative to the section start address, this resulted in
incorrect calculation of THREADPTR/$tp registers.
Fix by introducing new linker label, _flash_rodata_start, which points
to the .flash.rodata output section where TLS variables are located,
and use it when calculating THREADPTR/$tp.
Also remove the hardcoded rodata section alignment for Xtensa targets.
Alignment of rodata can be affected by the user application, which is
the issue dd849ffc was fixing. To accommodate any possible alignment,
save it in a linker label (_flash_rodata_align) and then use when
calculating THREADPTR. Note that this is not required on RISC-V, since
this target doesn't use TPOFF.
Noted as a problem with thread local storage returning a different task's
pointers, but some other were APIs also accessing current task unsafely.
Regression in FreeRTOS 10 update a3c90bf59a
Causes test added in parent commit to pass.
This race happens if the deleted task is running on the other CPU,
and is already spinning in a critical section waiting for xTaskQueueMutex
because it's about to be blocked for a resource.
The "deleted" task would end up blocked, possibly indefinitely, and
never actually deleted or its resources cleaned up by the idle tasks.
Details:
vTaskDelete() adds the target task to the xTasksWaitingTermination list,
expecting it to be yielded off CPU and then cleaned up later. However as soon as
vTaskDelete() releases xTaskQueueMutex, the target task runs and moves itself to the
xDelayedTaskList1. Because interrupts are already disabled on that CPU,
the "yield" to the other CPU sent by the vTaskDelete() comes afterward so
doesn't help.
Fixes issue with DPORT init task, this task uses minimum stack size and may not be
enough if stack smashing detection is set to Overall mode.
Also reworks the way we calculate minimum stack to allow for adding multiple
contributing factors.
Closes https://github.com/espressif/esp-idf/issues/6403
Unless the option for "assert and keep running" is enabled.
This means that silent asserts now work for FreeRTOS, and disabling asserts
now also disables them in FreeRTOS without needing a separate config change.
Related to https://github.com/espressif/esp-idf/issues/6306
NOP instructions have been added in order to prevent the code
from executing code it shouldn't execute. This is due to a delay
between the moment an interrupt is requested and the moment it
is fired. It only happens on RISC-V SoC.
