Jiang Jiang Jian
e3a5a85e2f
Merge branch 'feature/gcov_esp32c3_v4.4' into 'release/v4.4'
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debug_stubs and gcov: Refactor and add support for RISCV (v4.4)
See merge request espressif/esp-idf!17068
2022-02-16 03:26:49 +00:00
Alexey Gerenkov
1bbefc3e5d
debug_stubs: Refactor and add support for RISCV
2022-02-08 22:24:54 +03:00
songruojing
b80a070395
esp_system: replace the range comparsion for reset reason in perip clk init with specific reset reason check, also add a test case in LEDC to check for the perip clk not being disabled after cpu reset
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(cherry picked from commit f57456e9dd919e5eea1d3cd0caa64b5c97a4df73)
2022-01-27 09:51:00 +00:00
Konstantin Kondrashov
29f581fc70
freertos(esp32s3): SysTick uses systimer
2021-08-04 20:33:44 +08:00
Wangjialin
2b986fbd49
For esp_restart API, reset uart0 core first, then reset uart0 apb side, so as to prevent uart output garbage after cpu reset. (UART0 RST bits will be cleared in ROM)
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Add UART0/1 core reset on esp32c3, in case uart driver would also reset uart hardwares.
2021-07-21 11:41:04 +08:00
Omar Chebib
0771bd1711
espsystem: Rearchitecture and fix eh_frame_parser bugs
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eh_frame_parser is architecture independent, thus the files have
been rearchitectured. Some bugs have been fixed in the test.
A README file has also been added to eh_frame_parser host test
directory.
eh_frame_parser is now able to detect empty gaps in .eh_frame_hdr
table (missing DWARF information).
Fix a bug occuring when parsing backtraces originated from abort().
Fix build missing dependencies issue.
2021-07-15 12:47:51 +08:00
Omar Chebib
b967dc0dbf
espsystem: add support for RISC-V panic backtrace
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Add .eh_frame and .eh_frame_hdr sections to the binary (can be
enabled/disabled within menuconfig). These sections are parsed
when a panic occurs. Their DWARF instructions are decoded and
executed at runtime, to retrieve the whole backtrace. This
parser has been tested on both RISC-V and x86 architectures.
This feature needs esptool's merge adjacent ELF sections feature.
2021-07-13 15:42:40 +08:00
morris
1560d6f1ba
soc: add reset reasons in soc component
2021-07-13 10:45:38 +08:00
Michael (XIAO Xufeng)
a0d13a31ec
uart: fix misleading files for UART2
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Includes: header files, ld files and clk.c
ESP32-C3 only have UART0 and UART1.
2021-04-27 17:40:19 +08:00
Omar Chebib
bb9aa806f7
panic: handlers can now be placed in flash
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By unchecking "Place panic handler code in IRAM" in the menuconfig,
the panic handlers will be placed in flash. Of course, flash cache must
be activated when entering panic handlers.
2021-04-15 11:58:46 +08:00
Renz Bagaporo
8762bfebde
esp_system: move asysnc memcpy to esp_hw_support
2021-04-07 17:53:37 +08:00
Renz Bagaporo
a7bac58480
esp32: move system api to esp_system
2021-03-31 19:13:03 +08:00
Renz Bagaporo
7d85c42e52
esp32: move brownout and cache err int setup
2021-03-31 19:13:03 +08:00
KonstantinKondrashov
aa1338bf23
wdt: Fix timeout and RTC_SLOW_CLK
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RTC_SLOW_CLK
ESP32: 150kHz
ESP32-S2: 90kHz
ESP32-S3: 150kHz
ESP32-C3: 150kHz
2021-03-19 00:15:18 +08:00
Angus Gratton
fd164b82b6
Merge branch 'refactor/move_from_xtensa' into 'master'
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Movements from xtensa
Closes IDF-2164
See merge request espressif/esp-idf!10556
2021-03-11 00:24:25 +00:00
Angus Gratton
d6f4d99d93
core system: Fix warnings in compilation when assertions are disabled
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Adds a CI config for hello world that sets this, to catch future regressions
2021-03-03 10:26:57 +11:00
Renz Bagaporo
91a5770fd2
arch: move shared stack implementation to esp_system
2021-02-26 13:34:29 +08:00
Michael (XIAO Xufeng)
d7d1dee208
system: reset dma when soft reset
2021-01-25 04:51:40 +00:00
KonstantinKondrashov
dada7cd035
global: Uses CCOUNT API instead of XTHAL macro
2021-01-12 16:24:23 +08:00
Chen Jian Xing
5b44295cb9
esp_wifi: fix esp32c3 code issues
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1. enable wifi clk and rm dport header
2.syn phy_init_data.h from esp32
2021-01-10 16:16:28 +08:00
Angus Gratton
61c77d9212
esp_system: Add port-specific esp32c3 files
2020-12-24 13:40:01 +11:00
Angus Gratton
a5aac93051
esp_rom: Small changes for esp32c3 support
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Updated from internal commit 6d894813
2020-12-24 13:40:01 +11:00
