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esp32: move system api to esp_system

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This commit is contained in:
Renz Bagaporo 2021-03-11 09:48:30 +08:00
parent 393bd64a1e
commit a7bac58480
17 changed files with 70 additions and 112 deletions
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3
components/esp32/CMakeLists.txt
View File

@ -17,8 +17,7 @@ else()
"dport_access.c"
"esp_himem.c"
"spiram.c"
"spiram_psram.c"
"system_api_esp32.c")
"spiram_psram.c")
set(include_dirs "include")

3
components/esp32c3/CMakeLists.txt
View File

@ -16,8 +16,7 @@ else()
"esp_hmac.c"
"esp_ds.c"
"esp_crypto_lock.c"
"memprot.c"
"system_api_esp32c3.c")
"memprot.c")
set(include_dirs "include")
set(requires driver efuse soc riscv) #unfortunately rom/uart uses SOC registers directly

1
components/esp32s2/CMakeLists.txt
View File

@ -16,7 +16,6 @@ else()
"dport_access.c"
"spiram.c"
"spiram_psram.c"
"system_api_esp32s2.c"
"esp_crypto_lock.c"
"esp_hmac.c"
"esp_ds.c")

3
components/esp32s3/CMakeLists.txt
View File

@ -17,8 +17,7 @@ else()
"esp_crypto_lock.c"
"memprot.c"
"spiram.c"
"spiram_psram.c"
"system_api_esp32s3.c")
"spiram_psram.c")
set(include_dirs "include")
set(requires driver efuse soc xtensa) #unfortunately rom/uart uses SOC registers directly

3
components/esp_hw_support/port/esp32c3/CMakeLists.txt
View File

@ -4,8 +4,7 @@ set(srcs "cpu_util_esp32c3.c"
"rtc_init.c"
"rtc_pm.c"
"rtc_sleep.c"
"rtc_time.c"
)
"rtc_time.c")
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")

3
components/esp_hw_support/port/esp32s3/CMakeLists.txt
View File

@ -8,7 +8,8 @@ set(srcs
"rtc_pm.c"
"rtc_sleep.c"
"rtc_time.c"
"rtc_wdt.c")
"rtc_wdt.c"
)
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")

2
components/esp_system/CMakeLists.txt
View File

@ -17,7 +17,7 @@ else()
"int_wdt.c"
"esp_async_memcpy.c"
"panic.c"
"system_api.c"
"esp_system.c"
"startup.c"
"system_time.c"
"stack_check.c"

54
components/esp_system/system_api.c → components/esp_system/esp_system.c
View File

@ -1,3 +1,17 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "esp_system.h"
#include "esp_private/system_internal.h"
#include "esp_heap_caps.h"
@ -16,10 +30,29 @@
#include "esp32c3/memprot.h"
#endif
#define SHUTDOWN_HANDLERS_NO 4
static shutdown_handler_t shutdown_handlers[SHUTDOWN_HANDLERS_NO];
void IRAM_ATTR esp_restart_noos_dig(void)
{
// make sure all the panic handler output is sent from UART FIFO
if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
}
// switch to XTAL (otherwise we will keep running from the PLL)
rtc_clk_cpu_freq_set_xtal();
#if CONFIG_IDF_TARGET_ESP32
esp_cpu_unstall(PRO_CPU_NUM);
#endif
// reset the digital part
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
while (true) {
;
}
}
esp_err_t esp_register_shutdown_handler(shutdown_handler_t handler)
{
for (int i = 0; i < SHUTDOWN_HANDLERS_NO; i++) {
@ -44,25 +77,6 @@ esp_err_t esp_unregister_shutdown_handler(shutdown_handler_t handler)
return ESP_ERR_INVALID_STATE;
}
void IRAM_ATTR esp_restart_noos_dig(void)
{
// make sure all the panic handler output is sent from UART FIFO
if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
}
// switch to XTAL (otherwise we will keep running from the PLL)
rtc_clk_cpu_freq_set_xtal();
#if CONFIG_IDF_TARGET_ESP32
esp_cpu_unstall(PRO_CPU_NUM);
#endif
// reset the digital part
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
while (true) {
;
}
}
void IRAM_ATTR esp_restart(void)
{

2
components/esp_system/linker.lf
View File

@ -6,7 +6,7 @@ entries:
panic_arch (noflash)
reset_reason (noflash)
esp_err (noflash)
system_api:esp_system_abort (noflash)
esp_system:esp_system_abort (noflash)
if ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF:
usb_console:esp_usb_console_write_char (noflash)

1
components/esp_system/port/soc/esp32/CMakeLists.txt
View File

@ -1,6 +1,7 @@
set(srcs "dport_panic_highint_hdl.S"
"clk.c"
"reset_reason.c"
"system_internal.c"
"cache_err_int.c"
"../../arch/xtensa/panic_arch.c"
"../../arch/xtensa/panic_handler_asm.S"

42
components/esp32/system_api_esp32.c → components/esp_system/port/soc/esp32/system_internal.c
View File

@ -1,4 +1,4 @@
// Copyright 2013-2016 Espressif Systems (Shanghai) PTE LTD
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -19,7 +19,6 @@
#include "esp_efuse.h"
#include "esp_log.h"
#include "sdkconfig.h"
#include "esp32/rom/cache.h"
#include "esp_rom_uart.h"
#include "soc/dport_reg.h"
#include "soc/gpio_periph.h"
@ -32,6 +31,10 @@
#include "hal/cpu_hal.h"
#include "freertos/xtensa_api.h"
#include "soc/soc_memory_layout.h"
#include "cache_err_int.h"
#include "esp32/rom/cache.h"
#include "esp32/rom/rtc.h"
/* "inner" restart function for after RTOS, interrupts & anything else on this
* core are already stopped. Stalls other core, resets hardware,
@ -49,6 +52,8 @@ void IRAM_ATTR esp_restart_noos(void)
wdt_hal_write_protect_disable(&rtc_wdt_ctx);
wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
//Enable flash boot mode so that flash booting after restart is protected by the RTC WDT.
wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
@ -140,36 +145,3 @@ void IRAM_ATTR esp_restart_noos(void)
;
}
}
void esp_chip_info(esp_chip_info_t* out_info)
{
uint32_t efuse_rd3 = REG_READ(EFUSE_BLK0_RDATA3_REG);
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32;
out_info->revision = esp_efuse_get_chip_ver();
if ((efuse_rd3 & EFUSE_RD_CHIP_VER_DIS_APP_CPU_M) == 0) {
out_info->cores = 2;
} else {
out_info->cores = 1;
}
out_info->features = CHIP_FEATURE_WIFI_BGN;
if ((efuse_rd3 & EFUSE_RD_CHIP_VER_DIS_BT_M) == 0) {
out_info->features |= CHIP_FEATURE_BT | CHIP_FEATURE_BLE;
}
uint32_t package = esp_efuse_get_pkg_ver();
if (package == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 ||
package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 ||
package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 ||
package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) {
out_info->features |= CHIP_FEATURE_EMB_FLASH;
}
}
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
inline bool soc_has_cache_lock_bug(void)
{
return (esp_efuse_get_chip_ver() == 3);
}
#endif

1
components/esp_system/port/soc/esp32c3/CMakeLists.txt
View File

@ -1,5 +1,6 @@
set(srcs "clk.c"
"reset_reason.c"
"system_internal.c"
"cache_err_int.c"
"../../async_memcpy_impl_gdma.c"
"apb_backup_dma.c"

18
components/esp32c3/system_api_esp32c3.c → components/esp_system/port/soc/esp32c3/system_internal.c
View File

@ -1,4 +1,4 @@
// Copyright 2013-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -19,7 +19,6 @@
#include "esp_attr.h"
#include "esp_efuse.h"
#include "esp_log.h"
#include "esp32c3/rom/cache.h"
#include "riscv/riscv_interrupts.h"
#include "riscv/interrupt.h"
#include "esp_rom_uart.h"
@ -28,9 +27,14 @@
#include "soc/timer_group_reg.h"
#include "soc/cpu.h"
#include "soc/rtc.h"
#include "soc/rtc_periph.h"
#include "soc/syscon_reg.h"
#include "soc/system_reg.h"
#include "hal/wdt_hal.h"
#include "cache_err_int.h"
#include "esp32c3/rom/cache.h"
#include "esp32c3/rom/rtc.h"
/* "inner" restart function for after RTOS, interrupts & anything else on this
* core are already stopped. Stalls other core, resets hardware,
@ -96,6 +100,7 @@ void IRAM_ATTR esp_restart_noos(void)
SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST | BLE_REG_REST_BIT
|BLE_PWR_REG_REST_BIT | BLE_BB_REG_REST_BIT);
REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
// Reset timer/spi/uart
@ -137,12 +142,3 @@ void IRAM_ATTR esp_restart_noos(void)
;
}
}
void esp_chip_info(esp_chip_info_t *out_info)
{
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32C3;
out_info->revision = esp_efuse_get_chip_ver();
out_info->cores = 1;
out_info->features = CHIP_FEATURE_WIFI_BGN | CHIP_FEATURE_BLE;
}

1
components/esp_system/port/soc/esp32s2/CMakeLists.txt
View File

@ -2,6 +2,7 @@ set(srcs "async_memcpy_impl_cp_dma.c"
"dport_panic_highint_hdl.S"
"clk.c"
"reset_reason.c"
"system_internal.c"
"cache_err_int.c"
"../../arch/xtensa/panic_arch.c"
"../../arch/xtensa/panic_handler_asm.S"

28
components/esp32s2/system_api_esp32s2.c → components/esp_system/port/soc/esp32s2/system_internal.c
View File

@ -1,4 +1,4 @@
// Copyright 2013-2016 Espressif Systems (Shanghai) PTE LTD
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -28,10 +28,13 @@
#include "soc/cpu.h"
#include "soc/rtc.h"
#include "soc/syscon_reg.h"
#include "soc/rtc_periph.h"
#include "hal/wdt_hal.h"
#include "freertos/xtensa_api.h"
#include "hal/cpu_hal.h"
#include "esp32s2/rom/rtc.h"
/* "inner" restart function for after RTOS, interrupts & anything else on this
* core are already stopped. Stalls other core, resets hardware,
* triggers restart.
@ -110,26 +113,3 @@ void IRAM_ATTR esp_restart_noos(void)
;
}
}
void esp_chip_info(esp_chip_info_t *out_info)
{
uint32_t pkg_ver = esp_efuse_get_pkg_ver();
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32S2;
out_info->cores = 1;
out_info->features = CHIP_FEATURE_WIFI_BGN;
switch (pkg_ver) {
case 0: // ESP32-S2
break;
case 1: // ESP32-S2FH16
// fallthrough
case 2: // ESP32-S2FH32
out_info->features |= CHIP_FEATURE_EMB_FLASH;
break;
default: // New package, features unknown
break;
}
}

1
components/esp_system/port/soc/esp32s3/CMakeLists.txt
View File

@ -1,6 +1,7 @@
set(srcs "dport_panic_highint_hdl.S"
"clk.c"
"reset_reason.c"
"system_internal.c"
"cache_err_int.c"
"../../async_memcpy_impl_gdma.c"
"../../arch/xtensa/panic_arch.c"

16
components/esp32s3/system_api_esp32s3.c → components/esp_system/port/soc/esp32s3/system_internal.c
View File

@ -1,4 +1,5 @@
// Copyright 2013-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -18,7 +19,6 @@
#include "esp_private/system_internal.h"
#include "esp_attr.h"
#include "esp_log.h"
#include "esp32s3/rom/cache.h"
#include "esp_rom_uart.h"
#include "soc/dport_reg.h"
#include "soc/gpio_reg.h"
@ -27,9 +27,13 @@
#include "soc/cpu.h"
#include "soc/rtc.h"
#include "soc/syscon_reg.h"
#include "soc/rtc_periph.h"
#include "hal/wdt_hal.h"
#include "freertos/xtensa_api.h"
#include "esp32s3/rom/cache.h"
#include "esp32s3/rom/rtc.h"
/* "inner" restart function for after RTOS, interrupts & anything else on this
* core are already stopped. Stalls other core, resets hardware,
* triggers restart.
@ -139,11 +143,3 @@ void IRAM_ATTR esp_restart_noos(void)
;
}
}
void esp_chip_info(esp_chip_info_t *out_info)
{
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32S3;
out_info->cores = 2;
out_info->features = CHIP_FEATURE_WIFI_BGN;
}