13 Commits

Author	SHA1	Message	Date
Omar Chebib	5bcd9b2db8	G0: RISC-V targets have now an independent G0 layer ... G0 doesn't depend on any G1+ layer for RISC-V based targets	2022-06-14 15:00:53 +08:00
Marius Vikhammer	9362434c47	build-system: add property for architecture (riscv/xtensa) ... riscv/xtensa is now a common component.	2022-05-20 09:00:32 +08:00
laokaiyao	cf049e15ed	esp8684: rename target to esp32c2	2022-01-19 11:08:57 +08:00
Cao Sen Miao	36f6d16b8d	ESP8684: add soc, riscv, newlib support	2021-11-06 17:33:44 +08:00
Shu Chen	75bd02bd46	esp32h2: add some more fixes and TODOs	2021-07-01 20:36:39 +08:00
Shu Chen	ee23a489b9	esp32h2: code clean up	2021-07-01 19:53:50 +08:00
Shu Chen	2b9e8fed71	esp32h2: add esp32h2 build target ... Add esp32h2 support in the following components: * Kconfig * components/esptool_py * components/riscv * components/xtensa * tools	2021-07-01 19:51:33 +08:00
Renz Bagaporo	d920aa52be	xtensa: simplify build script	2021-02-26 19:45:48 +08:00
Renz Bagaporo	b1027005df	arch: move stdatomic	2021-02-26 18:40:00 +08:00
Renz Bagaporo	91a5770fd2	arch: move shared stack implementation to esp_system	2021-02-26 13:34:29 +08:00
morris	7a71cedf87	interrupt: filter out reserved int number by decoding risc-v JAL instruction	2021-01-05 15:39:46 +08:00
Felipe Neves	ec5acf91ee	esp_shared_stack: enable shared stack function for riscv and reenable the unit test	2021-01-05 15:39:46 +08:00
Angus Gratton	fccab8f4ef	riscv: Add new arch-level component ... Changes come from internal branch commit a6723fc	2020-11-12 09:33:18 +11:00