Commit Graph

9 Commits

Author SHA1 Message Date
Omar Chebib
8fae0f0753 G0: Support Xtensa targets for G0-only compilation
G0-only example now supports Xtensa targets. This means that G0 layer
does not depend on G1+ layers anymore
2022-06-20 11:34:20 +00:00
Omar Chebib
752026a174 Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master'
G0: RISC-V targets have now an independent G0 layer

See merge request espressif/esp-idf!17926
2022-06-16 11:53:39 +08:00
Omar Chebib
2fd784c97a G0 RISC-V: Remove "private_include/regi2c_brownout.h" header as it has been moved and simplify "regi2c_ctrl.h" 2022-06-14 15:00:53 +08:00
songruojing
6f6251f369 hal: Limit the HAL_ASSERTION_LEVEL in bootloader to be no larger than 1 (i.e. silent) 2022-06-13 17:47:51 +08:00
Omar Chebib
f772d78317 hal: Remove dependency on log component
hal component (G0) doesn't depend on log component (G1) anymore in G0-only applications.
2022-04-18 10:35:01 +08:00
Darian Leung
14fe6dcaaf HAL: Fix Force U32 macros for C++ typeof()
When using the Force U32 macros in C++, the peripheral structs will not
have copy constructors due to them being volatile. Thus, doing temp_reg = reg
via typeof() will not work and cause a "ambiguous overload of operator=" error.

This commit fixes the macros by reading the reg into a uint32_t value first.
2021-09-07 11:23:06 +08:00
SalimTerryLi
6af8d2edee
hal: remove usages of esp_log in HAL 2021-09-01 13:58:47 +08:00
SalimTerryLi
874a720286
soc/ll: workaround compiler bug that generate 8/16 bits inst instead of 32 bits one
update all struct headers to be more "standardized":

- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199

added helper macros to force peripheral registers being accessed in 32 bitwidth

added a check script into ci
2021-08-30 13:50:58 +08:00
morris
9afdf54748 hal: added HAL_ASSERT 2021-06-22 11:28:01 +08:00