mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
hal: added HAL_ASSERT
This commit is contained in:
morris
parent
ed428ab811
commit
9afdf54748
6
Kconfig
6
Kconfig
@ -270,6 +270,12 @@ mainmenu "Espressif IoT Development Framework Configuration"
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endchoice # assertions
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config COMPILER_OPTIMIZATION_ASSERTION_LEVEL
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int
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default 0 if COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE
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default 1 if COMPILER_OPTIMIZATION_ASSERTIONS_SILENT
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default 2 if COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE
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config COMPILER_OPTIMIZATION_CHECKS_SILENT
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bool "Disable messages in ESP_RETURN_ON_* and ESP_EXIT_ON_* macros"
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default n
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@ -2,7 +2,7 @@ idf_build_get_property(target IDF_TARGET)
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set(srcs "wdt_hal_iram.c"
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"mpu_hal.c")
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set(includes "${target}/include" "include")
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set(includes "${target}/include" "include" "platform_port/include")
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if(NOT BOOTLOADER_BUILD)
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list(APPEND srcs
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@ -105,3 +105,9 @@ idf_component_register(SRCS ${srcs}
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PRIV_INCLUDE_DIRS ${priv_include}
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REQUIRES soc
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LDFRAGMENTS linker.lf)
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if(CONFIG_HAL_DEFAULT_ASSERTION_LEVEL EQUAL 1)
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target_link_libraries(${COMPONENT_LIB} INTERFACE "-u abort")
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elseif(CONFIG_HAL_DEFAULT_ASSERTION_LEVEL EQUAL 2)
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target_link_libraries(${COMPONENT_LIB} INTERFACE "-u __assert_func")
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endif()
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33
components/hal/Kconfig
Normal file
33
components/hal/Kconfig
Normal file
@ -0,0 +1,33 @@
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menu "Hardware Abstraction Layer (HAL) and Low Level (LL)"
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choice HAL_DEFAULT_ASSERTION_LEVEL
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bool "Default HAL assertion level"
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default HAL_ASSERTION_EQUALS_SYSTEM
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help
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Set the assert behavior / level for HAL component.
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HAL component assert level can be set separately,
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but the level can't exceed the system assertion level.
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e.g. If the system assertion is disabled, then the HAL
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assertion can't be enabled either. If the system assertion
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is enable, then the HAL assertion can still be disabled
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by this Kconfig option.
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config HAL_ASSERTION_EQUALS_SYSTEM
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bool "Same as system assertion level"
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config HAL_ASSERTION_DISABLE
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bool "Disabled"
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depends on COMPILER_OPTIMIZATION_ASSERTION_LEVEL >= 0
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config HAL_ASSERTION_SILIENT
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bool "Silent"
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depends on COMPILER_OPTIMIZATION_ASSERTION_LEVEL >= 1
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config HAL_ASSERTION_ENABLE
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bool "Enabled"
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depends on COMPILER_OPTIMIZATION_ASSERTION_LEVEL >= 2
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endchoice
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config HAL_DEFAULT_ASSERTION_LEVEL
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int
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default COMPILER_OPTIMIZATION_ASSERTION_LEVEL if HAL_ASSERTION_EQUALS_SYSTEM
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default 0 if HAL_ASSERTION_DISABLE
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default 1 if HAL_ASSERTION_SILIENT
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default 2 if HAL_ASSERTION_ENABLE
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endmenu
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@ -12,11 +12,12 @@
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <sys/param.h>
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#include "soc/soc_caps.h"
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#include "hal/adc_hal.h"
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#include "hal/adc_hal_conf.h"
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#include "hal/assert.h"
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#include "sdkconfig.h"
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#include <sys/param.h>
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#if CONFIG_IDF_TARGET_ESP32C3
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@ -217,8 +218,8 @@ void adc_hal_fifo_reset(adc_hal_context_t *hal)
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static void adc_hal_digi_dma_link_descriptors(dma_descriptor_t *desc, uint8_t *data_buf, uint32_t size, uint32_t num)
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{
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assert(((uint32_t)data_buf % 4) == 0);
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assert((size % 4) == 0);
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HAL_ASSERT(((uint32_t)data_buf % 4) == 0);
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HAL_ASSERT((size % 4) == 0);
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uint32_t n = 0;
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while (num--) {
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@ -252,7 +253,7 @@ void adc_hal_digi_start(adc_hal_context_t *hal)
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adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_context_t *hal, const intptr_t eof_desc_addr, dma_descriptor_t **cur_desc)
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{
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assert(hal->cur_desc_ptr);
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HAL_ASSERT(hal->cur_desc_ptr);
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if (!hal->cur_desc_ptr->next) {
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return ADC_HAL_DMA_DESC_NULL;
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}
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@ -1,5 +1,5 @@
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COMPONENT_SRCDIRS := . esp32
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COMPONENT_ADD_INCLUDEDIRS := esp32/include include
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COMPONENT_ADD_INCLUDEDIRS := esp32/include include platform_port/include
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COMPONENT_ADD_LDFRAGMENTS += linker.lf
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COMPONENT_OBJEXCLUDE += ./spi_slave_hd_hal.o ./spi_flash_hal_gpspi.o ./spi_slave_hd_hal.o ./ds_hal.o ./gdma_hal.o ./lcd_hal.o ./systimer_hal.o ./usb_hal.o ./usbh_hal.o
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@ -17,6 +17,7 @@
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#include "hal/sha_types.h"
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#include "soc/hwcrypto_reg.h"
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#include "soc/dport_access.h"
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#include "hal/misc.h"
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#ifdef __cplusplus
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extern "C" {
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@ -123,7 +124,7 @@ static inline void sha_ll_fill_text_block(const void *input_text, size_t block_w
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reg_addr_buf = (uint32_t *)(SHA_TEXT_BASE);
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data_words = (uint32_t *)input_text;
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for (size_t i = 0; i < block_word_len; i++) {
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reg_addr_buf[i] = __builtin_bswap32(data_words[i]);
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reg_addr_buf[i] = HAL_SWAP32(data_words[i]);
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}
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}
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@ -22,12 +22,12 @@
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#pragma once
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#include "hal/hal_defs.h"
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#include "soc/spi_periph.h"
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#include "esp32/rom/lldesc.h"
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#include <string.h>
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#include <esp_types.h>
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#include <stdlib.h> //for abs()
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#include "esp_types.h"
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#include "esp32/rom/lldesc.h"
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#include "soc/spi_periph.h"
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#include "hal/misc.h"
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#ifdef __cplusplus
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extern "C" {
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@ -38,7 +38,7 @@ extern "C" {
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/// Interrupt not used. Don't use in app.
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#define SPI_LL_UNUSED_INT_MASK (SPI_INT_EN | SPI_SLV_WR_STA_DONE | SPI_SLV_RD_STA_DONE | SPI_SLV_WR_BUF_DONE | SPI_SLV_RD_BUF_DONE)
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/// Swap the bit order to its correct place to send
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#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)data<<(32-len))
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#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len))
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/// This is the expected clock frequency
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#define SPI_LL_PERIPH_CLK_FREQ (80 * 1000000)
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#define SPI_LL_GET_HW(ID) ((ID)==0? &SPI1:((ID)==1? &SPI2 : &SPI3))
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@ -22,6 +22,7 @@ extern "C" {
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#endif
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#include <stdlib.h>
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#include "hal/assert.h"
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#include "hal/timer_types.h"
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#include "soc/timer_periph.h"
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@ -43,7 +44,7 @@ _Static_assert(TIMER_INTR_WDT == TIMG_WDT_INT_CLR, "Add mapping to LL interrupt
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*/
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static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t divider)
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{
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assert(divider >= 2 && divider <= 65536);
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HAL_ASSERT(divider >= 2 && divider <= 65536);
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if (divider >= 65536) {
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divider = 0;
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}
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@ -29,6 +29,7 @@ extern "C" {
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#include <stdint.h>
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#include <stdbool.h>
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#include "sdkconfig.h"
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#include "hal/misc.h"
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#include "hal/twai_types.h"
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#include "soc/twai_periph.h"
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@ -574,8 +575,8 @@ static inline void twai_ll_set_tec(twai_dev_t *hw, uint32_t tec)
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*/
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static inline void twai_ll_set_acc_filter(twai_dev_t* hw, uint32_t code, uint32_t mask, bool single_filter)
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{
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uint32_t code_swapped = __builtin_bswap32(code);
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uint32_t mask_swapped = __builtin_bswap32(mask);
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uint32_t code_swapped = HAL_SWAP32(code);
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uint32_t mask_swapped = HAL_SWAP32(mask);
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for (int i = 0; i < 4; i++) {
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hw->acceptance_filter.acr[i].byte = ((code_swapped >> (i * 8)) & 0xFF);
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hw->acceptance_filter.amr[i].byte = ((mask_swapped >> (i * 8)) & 0xFF);
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@ -647,12 +648,12 @@ static inline void twai_ll_format_frame_buffer(uint32_t id, uint8_t dlc, const u
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//Set ID. The ID registers are big endian and left aligned, therefore a bswap will be required
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if (is_extd) {
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uint32_t id_temp = __builtin_bswap32((id & TWAI_EXTD_ID_MASK) << 3); //((id << 3) >> 8*(3-i))
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uint32_t id_temp = HAL_SWAP32((id & TWAI_EXTD_ID_MASK) << 3); //((id << 3) >> 8*(3-i))
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for (int i = 0; i < 4; i++) {
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tx_frame->extended.id[i] = (id_temp >> (8 * i)) & 0xFF;
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}
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} else {
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uint32_t id_temp = __builtin_bswap16((id & TWAI_STD_ID_MASK) << 5); //((id << 5) >> 8*(1-i))
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uint32_t id_temp = HAL_SWAP16((id & TWAI_STD_ID_MASK) << 5); //((id << 5) >> 8*(1-i))
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for (int i = 0; i < 2; i++) {
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tx_frame->standard.id[i] = (id_temp >> (8 * i)) & 0xFF;
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}
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@ -692,14 +693,14 @@ static inline void twai_ll_prase_frame_buffer(twai_ll_frame_buffer_t *rx_frame,
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for (int i = 0; i < 4; i++) {
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id_temp |= rx_frame->extended.id[i] << (8 * i);
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}
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id_temp = __builtin_bswap32(id_temp) >> 3; //((byte[i] << 8*(3-i)) >> 3)
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id_temp = HAL_SWAP32(id_temp) >> 3; //((byte[i] << 8*(3-i)) >> 3)
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*id = id_temp & TWAI_EXTD_ID_MASK;
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} else {
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uint32_t id_temp = 0;
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for (int i = 0; i < 2; i++) {
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id_temp |= rx_frame->standard.id[i] << (8 * i);
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}
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id_temp = __builtin_bswap16(id_temp) >> 5; //((byte[i] << 8*(1-i)) >> 5)
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id_temp = HAL_SWAP16(id_temp) >> 5; //((byte[i] << 8*(1-i)) >> 5)
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*id = id_temp & TWAI_STD_ID_MASK;
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}
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@ -16,6 +16,7 @@
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#include "soc/sensitive_reg.h"
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#include "soc/cache_memory.h"
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#include "hal/assert.h"
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#ifdef __cplusplus
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extern "C" {
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@ -96,7 +97,7 @@ static inline uint32_t memprot_ll_iram0_get_intr_source_num(void)
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static inline void memprot_ll_set_iram0_split_line(const void *line_addr, uint32_t sensitive_reg)
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{
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uint32_t addr = (uint32_t)line_addr;
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assert( addr >= IRAM0_SRAM_LEVEL_1_LOW && addr <= IRAM0_SRAM_LEVEL_3_HIGH );
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HAL_ASSERT(addr >= IRAM0_SRAM_LEVEL_1_LOW && addr <= IRAM0_SRAM_LEVEL_3_HIGH);
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uint32_t category[3] = {0};
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if (addr <= IRAM0_SRAM_LEVEL_1_HIGH) {
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@ -353,7 +354,7 @@ static inline uint32_t memprot_ll_dram0_get_intr_source_num(void)
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static inline void memprot_ll_set_dram0_split_line(const void *line_addr, uint32_t sensitive_reg)
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{
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uint32_t addr = (uint32_t)line_addr;
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assert( addr >= DRAM0_SRAM_LEVEL_1_LOW && addr <= DRAM0_SRAM_LEVEL_3_HIGH );
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HAL_ASSERT(addr >= DRAM0_SRAM_LEVEL_1_LOW && addr <= DRAM0_SRAM_LEVEL_3_HIGH);
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uint32_t category[3] = {0};
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if (addr <= DRAM0_SRAM_LEVEL_1_HIGH) {
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@ -20,12 +20,12 @@
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// The Lowlevel layer for SPI Flash Encryption.
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#include <stdbool.h>
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#include <string.h>
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#include "soc/system_reg.h"
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#include "soc/hwcrypto_reg.h"
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#include "soc/soc.h"
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#include "string.h"
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#include "assert.h"
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#include <stdbool.h>
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#include "hal/assert.h"
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#ifdef __cplusplus
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extern "C" {
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@ -67,7 +67,7 @@ static inline void spi_flash_encrypt_ll_disable(void)
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static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
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{
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// Our hardware only support flash encryption
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assert(type == FLASH_ENCRYPTION_MANU);
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HAL_ASSERT(type == FLASH_ENCRYPTION_MANU);
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REG_WRITE(AES_XTS_DESTINATION_REG, type);
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}
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@ -24,11 +24,12 @@
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#include <stdlib.h> //for abs()
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#include <string.h>
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#include "hal/hal_defs.h"
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#include "esp_attr.h"
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#include "esp_types.h"
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#include "soc/spi_periph.h"
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#include "esp32c3/rom/lldesc.h"
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#include "esp_attr.h"
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#include "soc/lldesc.h"
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#include "hal/assert.h"
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#include "hal/misc.h"
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#ifdef __cplusplus
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extern "C" {
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@ -37,7 +38,7 @@ extern "C" {
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/// Interrupt not used. Don't use in app.
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#define SPI_LL_UNUSED_INT_MASK (SPI_TRANS_DONE_INT_ENA | SPI_SLV_WR_DMA_DONE_INT_ENA | SPI_SLV_RD_DMA_DONE_INT_ENA | SPI_SLV_WR_BUF_DONE_INT_ENA | SPI_SLV_RD_BUF_DONE_INT_ENA)
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/// Swap the bit order to its correct place to send
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#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)data<<(32-len))
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#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len))
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/// This is the expected clock frequency
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#define SPI_LL_PERIPH_CLK_FREQ (80 * 1000000)
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#define SPI_LL_GET_HW(ID) ((ID)==0? ({abort();NULL;}):&GPSPI2)
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@ -351,9 +352,9 @@ static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_s
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*/
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static inline void spi_ll_write_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t *data, int len)
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{
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assert(byte_id+len <= 64);
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assert(len > 0);
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assert(byte_id >= 0);
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HAL_ASSERT(byte_id+len <= 64);
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HAL_ASSERT(len > 0);
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HAL_ASSERT(byte_id >= 0);
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while (len > 0) {
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uint32_t word;
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@ -15,8 +15,8 @@
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#include <stdint.h>
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#include <stdbool.h>
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#include <assert.h>
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#include "soc/systimer_struct.h"
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#include "hal/assert.h"
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#define SYSTIMER_LL_COUNTER_CLOCK (0) // Counter used for "wallclock" time
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#define SYSTIMER_LL_COUNTER_OS_TICK (1) // Counter used for OS tick
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@ -120,7 +120,7 @@ __attribute__((always_inline)) static inline void systimer_ll_enable_alarm_perio
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__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(systimer_dev_t *dev, uint32_t alarm_id, uint32_t period)
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{
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assert(period < (1 << 26));
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HAL_ASSERT(period < (1 << 26));
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dev->target_conf[alarm_id].target_period = period;
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}
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@ -22,8 +22,9 @@ extern "C" {
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#endif
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#include <stdlib.h>
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#include "hal/timer_types.h"
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#include "soc/timer_periph.h"
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#include "hal/timer_types.h"
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#include "hal/assert.h"
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_Static_assert(TIMER_INTR_T0 == TIMG_T0_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
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_Static_assert(TIMER_INTR_WDT == TIMG_WDT_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
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@ -47,7 +48,7 @@ typedef struct {
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*/
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static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t divider)
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{
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assert(divider >= 2 && divider <= 65536);
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HAL_ASSERT(divider >= 2 && divider <= 65536);
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if (divider >= 65536) {
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divider = 0;
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}
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@ -28,6 +28,7 @@ extern "C" {
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#include <stdint.h>
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#include <stdbool.h>
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#include "hal/misc.h"
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#include "hal/twai_types.h"
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#include "soc/twai_periph.h"
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@ -482,8 +483,8 @@ static inline void twai_ll_set_tec(twai_dev_t *hw, uint32_t tec)
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*/
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static inline void twai_ll_set_acc_filter(twai_dev_t* hw, uint32_t code, uint32_t mask, bool single_filter)
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{
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uint32_t code_swapped = __builtin_bswap32(code);
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uint32_t mask_swapped = __builtin_bswap32(mask);
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uint32_t code_swapped = HAL_SWAP32(code);
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uint32_t mask_swapped = HAL_SWAP32(mask);
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for (int i = 0; i < 4; i++) {
|
||||
hw->acceptance_filter.acr[i].byte = ((code_swapped >> (i * 8)) & 0xFF);
|
||||
hw->acceptance_filter.amr[i].byte = ((mask_swapped >> (i * 8)) & 0xFF);
|
||||
@ -555,12 +556,12 @@ static inline void twai_ll_format_frame_buffer(uint32_t id, uint8_t dlc, const u
|
||||
|
||||
//Set ID. The ID registers are big endian and left aligned, therefore a bswap will be required
|
||||
if (is_extd) {
|
||||
uint32_t id_temp = __builtin_bswap32((id & TWAI_EXTD_ID_MASK) << 3); //((id << 3) >> 8*(3-i))
|
||||
uint32_t id_temp = HAL_SWAP32((id & TWAI_EXTD_ID_MASK) << 3); //((id << 3) >> 8*(3-i))
|
||||
for (int i = 0; i < 4; i++) {
|
||||
tx_frame->extended.id[i] = (id_temp >> (8 * i)) & 0xFF;
|
||||
}
|
||||
} else {
|
||||
uint32_t id_temp = __builtin_bswap16((id & TWAI_STD_ID_MASK) << 5); //((id << 5) >> 8*(1-i))
|
||||
uint32_t id_temp = HAL_SWAP16((id & TWAI_STD_ID_MASK) << 5); //((id << 5) >> 8*(1-i))
|
||||
for (int i = 0; i < 2; i++) {
|
||||
tx_frame->standard.id[i] = (id_temp >> (8 * i)) & 0xFF;
|
||||
}
|
||||
@ -600,14 +601,14 @@ static inline void twai_ll_prase_frame_buffer(twai_ll_frame_buffer_t *rx_frame,
|
||||
for (int i = 0; i < 4; i++) {
|
||||
id_temp |= rx_frame->extended.id[i] << (8 * i);
|
||||
}
|
||||
id_temp = __builtin_bswap32(id_temp) >> 3; //((byte[i] << 8*(3-i)) >> 3)
|
||||
id_temp = HAL_SWAP32(id_temp) >> 3; //((byte[i] << 8*(3-i)) >> 3)
|
||||
*id = id_temp & TWAI_EXTD_ID_MASK;
|
||||
} else {
|
||||
uint32_t id_temp = 0;
|
||||
for (int i = 0; i < 2; i++) {
|
||||
id_temp |= rx_frame->standard.id[i] << (8 * i);
|
||||
}
|
||||
id_temp = __builtin_bswap16(id_temp) >> 5; //((byte[i] << 8*(1-i)) >> 5)
|
||||
id_temp = HAL_SWAP16(id_temp) >> 5; //((byte[i] << 8*(1-i)) >> 5)
|
||||
*id = id_temp & TWAI_STD_ID_MASK;
|
||||
}
|
||||
|
||||
|
||||
@ -14,10 +14,10 @@
|
||||
|
||||
// The HAL layer for RTC CNTL (common part)
|
||||
|
||||
#include "hal/rtc_hal.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "esp32c3/rom/lldesc.h"
|
||||
#include "esp_attr.h"
|
||||
#include "soc/lldesc.h"
|
||||
#include "hal/rtc_hal.h"
|
||||
#include "hal/assert.h"
|
||||
|
||||
#define RTC_CNTL_HAL_LINK_BUF_SIZE_MIN (SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE) /* The minimum size of dma link buffer */
|
||||
|
||||
@ -27,9 +27,9 @@ typedef struct rtc_cntl_link_buf_conf {
|
||||
|
||||
void * rtc_cntl_hal_dma_link_init(void *elem, void *buff, int size, void *next)
|
||||
{
|
||||
assert(elem != NULL);
|
||||
assert(buff != NULL);
|
||||
assert(size >= RTC_CNTL_HAL_LINK_BUF_SIZE_MIN);
|
||||
HAL_ASSERT(elem != NULL);
|
||||
HAL_ASSERT(buff != NULL);
|
||||
HAL_ASSERT(size >= RTC_CNTL_HAL_LINK_BUF_SIZE_MIN);
|
||||
|
||||
lldesc_t *plink = (lldesc_t *)elem;
|
||||
|
||||
|
||||
@ -14,6 +14,8 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "hal/assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
@ -149,7 +151,7 @@ static inline bool esp_memprot_iram0_sram_is_intr_mine(void)
|
||||
//block 0-3
|
||||
static inline void esp_memprot_iram0_sram_set_uni_block_perm(uint32_t block, bool write_perm, bool read_perm, bool exec_perm)
|
||||
{
|
||||
assert(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS);
|
||||
HAL_ASSERT(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS);
|
||||
|
||||
uint32_t write_bit, read_bit, exec_bit;
|
||||
switch (block) {
|
||||
@ -198,7 +200,7 @@ static inline void esp_memprot_iram0_sram_set_uni_block_perm(uint32_t block, boo
|
||||
|
||||
static inline uint32_t esp_memprot_iram0_sram_get_uni_block_read_bit(uint32_t block)
|
||||
{
|
||||
assert(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS);
|
||||
HAL_ASSERT(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS);
|
||||
|
||||
switch (block) {
|
||||
case IRAM0_SRAM_UNI_BLOCK_0:
|
||||
@ -216,7 +218,7 @@ static inline uint32_t esp_memprot_iram0_sram_get_uni_block_read_bit(uint32_t bl
|
||||
|
||||
static inline uint32_t esp_memprot_iram0_sram_get_uni_block_write_bit(uint32_t block)
|
||||
{
|
||||
assert(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS);
|
||||
HAL_ASSERT(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS);
|
||||
|
||||
switch (block) {
|
||||
case IRAM0_SRAM_UNI_BLOCK_0:
|
||||
@ -234,7 +236,7 @@ static inline uint32_t esp_memprot_iram0_sram_get_uni_block_write_bit(uint32_t b
|
||||
|
||||
static inline uint32_t esp_memprot_iram0_sram_get_uni_block_exec_bit(uint32_t block)
|
||||
{
|
||||
assert(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS);
|
||||
HAL_ASSERT(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS);
|
||||
|
||||
switch (block) {
|
||||
case IRAM0_SRAM_UNI_BLOCK_0:
|
||||
@ -252,7 +254,7 @@ static inline uint32_t esp_memprot_iram0_sram_get_uni_block_exec_bit(uint32_t bl
|
||||
|
||||
static inline void esp_memprot_iram0_sram_get_uni_block_sgnf_bits(uint32_t block, uint32_t *write_bit, uint32_t *read_bit, uint32_t *exec_bit)
|
||||
{
|
||||
assert(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS);
|
||||
HAL_ASSERT(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS);
|
||||
|
||||
switch (block) {
|
||||
case IRAM0_SRAM_UNI_BLOCK_0:
|
||||
@ -293,8 +295,8 @@ static inline uint32_t esp_memprot_iram0_sram_get_perm_split_reg(void)
|
||||
static inline void esp_memprot_iram0_sram_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx)
|
||||
{
|
||||
uint32_t addr = (uint32_t)split_addr;
|
||||
assert(addr <= IRAM0_SRAM_SPL_BLOCK_HIGH);
|
||||
assert(addr % 0x4 == 0);
|
||||
HAL_ASSERT(addr <= IRAM0_SRAM_SPL_BLOCK_HIGH);
|
||||
HAL_ASSERT(addr % 0x4 == 0);
|
||||
|
||||
//find possible split.address in low region blocks
|
||||
int uni_blocks_low = -1;
|
||||
@ -437,7 +439,7 @@ static inline uint32_t esp_memprot_iram0_rtcfast_get_perm_split_reg(void)
|
||||
static inline void esp_memprot_iram0_rtcfast_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx)
|
||||
{
|
||||
uint32_t addr = (uint32_t)split_addr;
|
||||
assert( addr % 0x4 == 0 );
|
||||
HAL_ASSERT(addr % 0x4 == 0);
|
||||
|
||||
//conf reg [10:0]
|
||||
uint32_t reg_split_addr = IRAM0_RTCFAST_ADDR_TO_CONF_REG(addr);
|
||||
@ -626,7 +628,7 @@ static inline bool esp_memprot_dram0_sram_is_intr_mine(void)
|
||||
|
||||
static inline void esp_memprot_dram0_sram_get_uni_block_sgnf_bits(uint32_t block, uint32_t *write_bit, uint32_t *read_bit)
|
||||
{
|
||||
assert(block < DRAM0_SRAM_TOTAL_UNI_BLOCKS);
|
||||
HAL_ASSERT(block < DRAM0_SRAM_TOTAL_UNI_BLOCKS);
|
||||
|
||||
switch (block) {
|
||||
case DRAM0_SRAM_UNI_BLOCK_0:
|
||||
@ -652,7 +654,7 @@ static inline void esp_memprot_dram0_sram_get_uni_block_sgnf_bits(uint32_t block
|
||||
|
||||
static inline void esp_memprot_dram0_sram_set_uni_block_perm(uint32_t block, bool write_perm, bool read_perm)
|
||||
{
|
||||
assert(block < DRAM0_SRAM_TOTAL_UNI_BLOCKS);
|
||||
HAL_ASSERT(block < DRAM0_SRAM_TOTAL_UNI_BLOCKS);
|
||||
|
||||
uint32_t write_bit, read_bit;
|
||||
esp_memprot_dram0_sram_get_uni_block_sgnf_bits(block, &write_bit, &read_bit);
|
||||
@ -672,7 +674,7 @@ static inline void esp_memprot_dram0_sram_set_uni_block_perm(uint32_t block, boo
|
||||
|
||||
static inline uint32_t esp_memprot_dram0_sram_get_uni_block_read_bit(uint32_t block)
|
||||
{
|
||||
assert(block < DRAM0_SRAM_TOTAL_UNI_BLOCKS);
|
||||
HAL_ASSERT(block < DRAM0_SRAM_TOTAL_UNI_BLOCKS);
|
||||
|
||||
switch (block) {
|
||||
case DRAM0_SRAM_UNI_BLOCK_0:
|
||||
@ -690,7 +692,7 @@ static inline uint32_t esp_memprot_dram0_sram_get_uni_block_read_bit(uint32_t bl
|
||||
|
||||
static inline uint32_t esp_memprot_dram0_sram_get_uni_block_write_bit(uint32_t block)
|
||||
{
|
||||
assert(block < DRAM0_SRAM_TOTAL_UNI_BLOCKS);
|
||||
HAL_ASSERT(block < DRAM0_SRAM_TOTAL_UNI_BLOCKS);
|
||||
|
||||
switch (block) {
|
||||
case DRAM0_SRAM_UNI_BLOCK_0:
|
||||
@ -717,8 +719,8 @@ static inline void esp_memprot_dram0_sram_set_prot(uint32_t *split_addr, bool lw
|
||||
uint32_t addr = (uint32_t)split_addr;
|
||||
|
||||
//low boundary check provided by LD script. see comment in esp_memprot_iram0_sram_set_prot()
|
||||
assert( addr <= DRAM0_SRAM_SPL_BLOCK_HIGH );
|
||||
assert( addr % 0x4 == 0 );
|
||||
HAL_ASSERT(addr <= DRAM0_SRAM_SPL_BLOCK_HIGH);
|
||||
HAL_ASSERT(addr % 0x4 == 0 );
|
||||
|
||||
//set low region
|
||||
int uni_blocks_low = -1;
|
||||
@ -828,7 +830,7 @@ static inline bool esp_memprot_dram0_rtcfast_is_intr_mine(void)
|
||||
static inline void esp_memprot_dram0_rtcfast_set_prot(uint32_t *split_addr, bool lw, bool lr, bool hw, bool hr)
|
||||
{
|
||||
uint32_t addr = (uint32_t)split_addr;
|
||||
assert( addr % 0x4 == 0 );
|
||||
HAL_ASSERT(addr % 0x4 == 0);
|
||||
|
||||
//conf reg [10:0]
|
||||
uint32_t reg_split_addr = DRAM0_RTCFAST_ADDR_TO_CONF_REG( addr );
|
||||
|
||||
@ -14,6 +14,8 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "hal/assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
@ -140,7 +142,7 @@ static inline bool esp_memprot_peri1_rtcslow_is_intr_mine(void)
|
||||
static inline void esp_memprot_peri1_rtcslow_set_prot(uint32_t *split_addr, bool lw, bool lr, bool hw, bool hr)
|
||||
{
|
||||
uint32_t addr = (uint32_t)split_addr;
|
||||
assert( addr % 0x4 == 0 );
|
||||
HAL_ASSERT(addr % 0x4 == 0);
|
||||
|
||||
uint32_t reg_split_addr = PERI1_RTCSLOW_ADDR_TO_CONF_REG(addr);
|
||||
|
||||
@ -302,7 +304,7 @@ static inline bool esp_memprot_peri2_rtcslow_0_is_intr_mine(void)
|
||||
static inline void esp_memprot_peri2_rtcslow_0_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx)
|
||||
{
|
||||
uint32_t addr = (uint32_t)split_addr;
|
||||
assert( addr % 0x4 == 0 );
|
||||
HAL_ASSERT(addr % 0x4 == 0);
|
||||
|
||||
uint32_t reg_split_addr = PERI2_RTCSLOW_0_ADDR_TO_CONF_REG(addr);
|
||||
|
||||
@ -387,7 +389,7 @@ static inline bool esp_memprot_peri2_rtcslow_1_is_intr_mine(void)
|
||||
static inline void esp_memprot_peri2_rtcslow_1_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx)
|
||||
{
|
||||
uint32_t addr = (uint32_t)split_addr;
|
||||
assert( addr % 0x4 == 0 );
|
||||
HAL_ASSERT(addr % 0x4 == 0);
|
||||
|
||||
uint32_t reg_split_addr = PERI2_RTCSLOW_1_ADDR_TO_CONF_REG(addr);
|
||||
|
||||
|
||||
@ -20,12 +20,12 @@
|
||||
|
||||
// The Lowlevel layer for SPI Flash Encryption.
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <string.h>
|
||||
#include "soc/system_reg.h"
|
||||
#include "soc/hwcrypto_reg.h"
|
||||
#include "soc/soc.h"
|
||||
#include "string.h"
|
||||
#include "assert.h"
|
||||
#include <stdbool.h>
|
||||
#include "hal/assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@ -77,7 +77,7 @@ static inline void spi_flash_encrypt_ll_disable(void)
|
||||
static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
|
||||
{
|
||||
// Our hardware only support flash encryption
|
||||
assert(type == FLASH_ENCRYPTION_MANU);
|
||||
HAL_ASSERT(type == FLASH_ENCRYPTION_MANU);
|
||||
REG_WRITE(AES_XTS_DESTINATION_REG, type);
|
||||
}
|
||||
|
||||
|
||||
@ -24,11 +24,12 @@
|
||||
|
||||
#include <stdlib.h> //for abs()
|
||||
#include <string.h>
|
||||
#include "hal/hal_defs.h"
|
||||
#include "esp_types.h"
|
||||
#include "soc/spi_periph.h"
|
||||
#include "esp32s2/rom/lldesc.h"
|
||||
#include "esp_attr.h"
|
||||
#include "soc/spi_periph.h"
|
||||
#include "soc/lldesc.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/misc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@ -39,7 +40,7 @@ extern "C" {
|
||||
/// Interrupt not used. Don't use in app.
|
||||
#define SPI_LL_UNUSED_INT_MASK (SPI_INT_TRANS_DONE_EN | SPI_INT_WR_DMA_DONE_EN | SPI_INT_RD_DMA_DONE_EN | SPI_INT_WR_BUF_DONE_EN | SPI_INT_RD_BUF_DONE_EN)
|
||||
/// Swap the bit order to its correct place to send
|
||||
#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)data<<(32-len))
|
||||
#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len))
|
||||
/// This is the expected clock frequency
|
||||
#define SPI_LL_PERIPH_CLK_FREQ (80 * 1000000)
|
||||
#define SPI_LL_GET_HW(ID) ((ID)==0? ({abort();NULL;}):((ID)==1? &GPSPI2 : &GPSPI3))
|
||||
@ -360,9 +361,9 @@ static inline void spi_ll_read_buffer_byte(spi_dev_t *hw, int byte_addr, uint8_t
|
||||
|
||||
static inline void spi_ll_write_buffer_byte(spi_dev_t *hw, int byte_addr, uint8_t *data, int len)
|
||||
{
|
||||
assert( byte_addr + len <= 72);
|
||||
assert(len > 0);
|
||||
assert(byte_addr >= 0);
|
||||
HAL_ASSERT(byte_addr + len <= 72);
|
||||
HAL_ASSERT(len > 0);
|
||||
HAL_ASSERT(byte_addr >= 0);
|
||||
|
||||
while (len > 0) {
|
||||
uint32_t word;
|
||||
@ -1088,7 +1089,7 @@ static inline void spi_dma_ll_rx_reset(spi_dma_dev_t *dma_in, uint32_t channel)
|
||||
{
|
||||
//Reset RX DMA peripheral
|
||||
dma_in->dma_in_link.dma_rx_ena = 0;
|
||||
assert(dma_in->dma_in_link.dma_rx_ena == 0);
|
||||
HAL_ASSERT(dma_in->dma_in_link.dma_rx_ena == 0);
|
||||
|
||||
dma_in->dma_conf.in_rst = 1;
|
||||
dma_in->dma_conf.in_rst = 0;
|
||||
|
||||
@ -15,8 +15,8 @@
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <assert.h>
|
||||
#include "soc/systimer_struct.h"
|
||||
#include "hal/assert.h"
|
||||
|
||||
#define SYSTIMER_LL_COUNTER_CLOCK (0) // Counter used for "wallclock" time
|
||||
#define SYSTIMER_LL_ALARM_CLOCK (2) // Alarm used for "wallclock" time
|
||||
@ -131,7 +131,7 @@ __attribute__((always_inline)) static inline void systimer_ll_enable_alarm_perio
|
||||
|
||||
__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(systimer_dev_t *dev, uint32_t alarm_id, uint32_t period)
|
||||
{
|
||||
assert(period < (1 << 30));
|
||||
HAL_ASSERT(period < (1 << 30));
|
||||
dev->target_conf[alarm_id].target_period = period;
|
||||
}
|
||||
|
||||
|
||||
@ -22,8 +22,9 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdlib.h>
|
||||
#include "hal/timer_types.h"
|
||||
#include "soc/timer_periph.h"
|
||||
#include "hal/timer_types.h"
|
||||
#include "hal/assert.h"
|
||||
|
||||
_Static_assert(TIMER_INTR_T0 == TIMG_T0_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
|
||||
_Static_assert(TIMER_INTR_T1 == TIMG_T1_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
|
||||
@ -43,7 +44,7 @@ _Static_assert(TIMER_INTR_WDT == TIMG_WDT_INT_CLR, "Add mapping to LL interrupt
|
||||
*/
|
||||
static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t divider)
|
||||
{
|
||||
assert(divider >= 2 && divider <= 65536);
|
||||
HAL_ASSERT(divider >= 2 && divider <= 65536);
|
||||
if (divider >= 65536) {
|
||||
divider = 0;
|
||||
}
|
||||
|
||||
@ -28,6 +28,7 @@ extern "C" {
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "hal/misc.h"
|
||||
#include "hal/twai_types.h"
|
||||
#include "soc/twai_periph.h"
|
||||
|
||||
@ -482,8 +483,8 @@ static inline void twai_ll_set_tec(twai_dev_t *hw, uint32_t tec)
|
||||
*/
|
||||
static inline void twai_ll_set_acc_filter(twai_dev_t* hw, uint32_t code, uint32_t mask, bool single_filter)
|
||||
{
|
||||
uint32_t code_swapped = __builtin_bswap32(code);
|
||||
uint32_t mask_swapped = __builtin_bswap32(mask);
|
||||
uint32_t code_swapped = HAL_SWAP32(code);
|
||||
uint32_t mask_swapped = HAL_SWAP32(mask);
|
||||
for (int i = 0; i < 4; i++) {
|
||||
hw->acceptance_filter.acr[i].byte = ((code_swapped >> (i * 8)) & 0xFF);
|
||||
hw->acceptance_filter.amr[i].byte = ((mask_swapped >> (i * 8)) & 0xFF);
|
||||
@ -555,12 +556,12 @@ static inline void twai_ll_format_frame_buffer(uint32_t id, uint8_t dlc, const u
|
||||
|
||||
//Set ID. The ID registers are big endian and left aligned, therefore a bswap will be required
|
||||
if (is_extd) {
|
||||
uint32_t id_temp = __builtin_bswap32((id & TWAI_EXTD_ID_MASK) << 3); //((id << 3) >> 8*(3-i))
|
||||
uint32_t id_temp = HAL_SWAP32((id & TWAI_EXTD_ID_MASK) << 3); //((id << 3) >> 8*(3-i))
|
||||
for (int i = 0; i < 4; i++) {
|
||||
tx_frame->extended.id[i] = (id_temp >> (8 * i)) & 0xFF;
|
||||
}
|
||||
} else {
|
||||
uint32_t id_temp = __builtin_bswap16((id & TWAI_STD_ID_MASK) << 5); //((id << 5) >> 8*(1-i))
|
||||
uint32_t id_temp = HAL_SWAP16((id & TWAI_STD_ID_MASK) << 5); //((id << 5) >> 8*(1-i))
|
||||
for (int i = 0; i < 2; i++) {
|
||||
tx_frame->standard.id[i] = (id_temp >> (8 * i)) & 0xFF;
|
||||
}
|
||||
@ -600,14 +601,14 @@ static inline void twai_ll_prase_frame_buffer(twai_ll_frame_buffer_t *rx_frame,
|
||||
for (int i = 0; i < 4; i++) {
|
||||
id_temp |= rx_frame->extended.id[i] << (8 * i);
|
||||
}
|
||||
id_temp = __builtin_bswap32(id_temp) >> 3; //((byte[i] << 8*(3-i)) >> 3)
|
||||
id_temp = HAL_SWAP32(id_temp) >> 3; //((byte[i] << 8*(3-i)) >> 3)
|
||||
*id = id_temp & TWAI_EXTD_ID_MASK;
|
||||
} else {
|
||||
uint32_t id_temp = 0;
|
||||
for (int i = 0; i < 2; i++) {
|
||||
id_temp |= rx_frame->standard.id[i] << (8 * i);
|
||||
}
|
||||
id_temp = __builtin_bswap16(id_temp) >> 5; //((byte[i] << 8*(1-i)) >> 5)
|
||||
id_temp = HAL_SWAP16(id_temp) >> 5; //((byte[i] << 8*(1-i)) >> 5)
|
||||
*id = id_temp & TWAI_STD_ID_MASK;
|
||||
}
|
||||
|
||||
|
||||
@ -15,9 +15,9 @@
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <assert.h>
|
||||
#include "soc/lcd_cam_reg.h"
|
||||
#include "soc/lcd_cam_struct.h"
|
||||
#include "hal/assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@ -45,7 +45,7 @@ static inline void lcd_ll_enable_clock(lcd_cam_dev_t *dev, bool en)
|
||||
static inline void lcd_ll_set_group_clock_src(lcd_cam_dev_t *dev, int src, int div_num, int div_a, int div_b)
|
||||
{
|
||||
// lcd_clk = module_clock_src / (div_num + div_b / div_a)
|
||||
assert(div_num >= 2);
|
||||
HAL_ASSERT(div_num >= 2);
|
||||
dev->lcd_clock.lcd_clk_sel = src;
|
||||
dev->lcd_clock.lcd_clkm_div_num = div_num;
|
||||
dev->lcd_clock.lcd_clkm_div_a = div_a;
|
||||
@ -76,7 +76,7 @@ static inline void lcd_ll_enable_rgb_yuv_convert(lcd_cam_dev_t *dev, bool en)
|
||||
|
||||
static inline void lcd_ll_set_phase_cycles(lcd_cam_dev_t *dev, uint32_t cmd_cycles, uint32_t dummy_cycles, uint32_t data_cycles)
|
||||
{
|
||||
assert(cmd_cycles <= 2);
|
||||
HAL_ASSERT(cmd_cycles <= 2);
|
||||
dev->lcd_user.lcd_cmd = (cmd_cycles > 0);
|
||||
dev->lcd_user.lcd_dummy = (dummy_cycles > 0);
|
||||
dev->lcd_user.lcd_dout = (data_cycles > 0);
|
||||
|
||||
@ -14,6 +14,8 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "hal/assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
@ -133,7 +135,7 @@ static inline uint32_t esp_memprot_iram0_get_lock_bit(void)
|
||||
//block 0-3
|
||||
static inline void esp_memprot_iram0_set_uni_block_perm(uint32_t block, bool write_perm, bool read_perm, bool exec_perm)
|
||||
{
|
||||
assert(block < IRAM0_TOTAL_UNI_BLOCKS);
|
||||
HAL_ASSERT(block < IRAM0_TOTAL_UNI_BLOCKS);
|
||||
|
||||
uint32_t write_bit, read_bit, exec_bit;
|
||||
switch ( block ) {
|
||||
@ -182,7 +184,7 @@ static inline void esp_memprot_iram0_set_uni_block_perm(uint32_t block, bool wri
|
||||
|
||||
static inline uint32_t esp_memprot_iram0_get_uni_block_read_bit(uint32_t block)
|
||||
{
|
||||
assert(block < IRAM0_TOTAL_UNI_BLOCKS);
|
||||
HAL_ASSERT(block < IRAM0_TOTAL_UNI_BLOCKS);
|
||||
|
||||
switch ( block ) {
|
||||
case IRAM0_UNI_BLOCK_0:
|
||||
@ -200,7 +202,7 @@ static inline uint32_t esp_memprot_iram0_get_uni_block_read_bit(uint32_t block)
|
||||
|
||||
static inline uint32_t esp_memprot_iram0_get_uni_block_write_bit(uint32_t block)
|
||||
{
|
||||
assert(block < IRAM0_TOTAL_UNI_BLOCKS);
|
||||
HAL_ASSERT(block < IRAM0_TOTAL_UNI_BLOCKS);
|
||||
|
||||
switch ( block ) {
|
||||
case IRAM0_UNI_BLOCK_0:
|
||||
@ -218,7 +220,7 @@ static inline uint32_t esp_memprot_iram0_get_uni_block_write_bit(uint32_t block)
|
||||
|
||||
static inline uint32_t esp_memprot_iram0_get_uni_block_exec_bit(uint32_t block)
|
||||
{
|
||||
assert(block < IRAM0_TOTAL_UNI_BLOCKS);
|
||||
HAL_ASSERT(block < IRAM0_TOTAL_UNI_BLOCKS);
|
||||
|
||||
switch ( block ) {
|
||||
case IRAM0_UNI_BLOCK_0:
|
||||
@ -236,7 +238,7 @@ static inline uint32_t esp_memprot_iram0_get_uni_block_exec_bit(uint32_t block)
|
||||
|
||||
static inline void esp_memprot_iram0_get_uni_block_sgnf_bits(uint32_t block, uint32_t *write_bit, uint32_t *read_bit, uint32_t *exec_bit)
|
||||
{
|
||||
assert(block < IRAM0_TOTAL_UNI_BLOCKS);
|
||||
HAL_ASSERT(block < IRAM0_TOTAL_UNI_BLOCKS);
|
||||
|
||||
switch ( block ) {
|
||||
case IRAM0_UNI_BLOCK_0:
|
||||
@ -277,7 +279,7 @@ static inline uint32_t esp_memprot_iram0_get_perm_split_reg(void)
|
||||
static inline void esp_memprot_iram0_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx)
|
||||
{
|
||||
uint32_t addr = (uint32_t)split_addr;
|
||||
assert( addr <= IRAM0_SPL_BLOCK_HIGH );
|
||||
HAL_ASSERT(addr <= IRAM0_SPL_BLOCK_HIGH);
|
||||
|
||||
//find possible split.address in low region blocks
|
||||
int uni_blocks_low = -1;
|
||||
@ -330,7 +332,7 @@ static inline void esp_memprot_iram0_set_prot(uint32_t *split_addr, bool lw, boo
|
||||
|
||||
//split Address must be WORD aligned
|
||||
reg_split_addr = addr >> 2;
|
||||
assert(addr == (reg_split_addr << 2));
|
||||
HAL_ASSERT(addr == (reg_split_addr << 2));
|
||||
|
||||
//use only 17 signf.bits as the cropped parts are constant for whole section (bits [16:0])
|
||||
reg_split_addr = (reg_split_addr << DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR_S) & DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR_M;
|
||||
@ -453,7 +455,7 @@ static inline uint32_t esp_memprot_dram0_get_lock_bit(void)
|
||||
|
||||
static inline void esp_memprot_dram0_get_uni_block_sgnf_bits(uint32_t block, uint32_t *write_bit, uint32_t *read_bit)
|
||||
{
|
||||
assert(block < DRAM0_TOTAL_UNI_BLOCKS);
|
||||
HAL_ASSERT(block < DRAM0_TOTAL_UNI_BLOCKS);
|
||||
|
||||
switch ( block ) {
|
||||
case DRAM0_UNI_BLOCK_0:
|
||||
@ -479,7 +481,7 @@ static inline void esp_memprot_dram0_get_uni_block_sgnf_bits(uint32_t block, uin
|
||||
|
||||
static inline void esp_memprot_dram0_set_uni_block_perm(uint32_t block, bool write_perm, bool read_perm)
|
||||
{
|
||||
assert(block < DRAM0_TOTAL_UNI_BLOCKS);
|
||||
HAL_ASSERT(block < DRAM0_TOTAL_UNI_BLOCKS);
|
||||
|
||||
uint32_t write_bit, read_bit;
|
||||
esp_memprot_dram0_get_uni_block_sgnf_bits(block, &write_bit, &read_bit);
|
||||
@ -499,7 +501,7 @@ static inline void esp_memprot_dram0_set_uni_block_perm(uint32_t block, bool wri
|
||||
|
||||
static inline uint32_t esp_memprot_dram0_get_uni_block_read_bit(uint32_t block)
|
||||
{
|
||||
assert(block < DRAM0_TOTAL_UNI_BLOCKS);
|
||||
HAL_ASSERT(block < DRAM0_TOTAL_UNI_BLOCKS);
|
||||
|
||||
switch ( block ) {
|
||||
case DRAM0_UNI_BLOCK_0:
|
||||
@ -517,7 +519,7 @@ static inline uint32_t esp_memprot_dram0_get_uni_block_read_bit(uint32_t block)
|
||||
|
||||
static inline uint32_t esp_memprot_dram0_get_uni_block_write_bit(uint32_t block)
|
||||
{
|
||||
assert(block < DRAM0_TOTAL_UNI_BLOCKS);
|
||||
HAL_ASSERT(block < DRAM0_TOTAL_UNI_BLOCKS);
|
||||
|
||||
switch ( block ) {
|
||||
case DRAM0_UNI_BLOCK_0:
|
||||
@ -575,7 +577,7 @@ static inline void esp_memprot_dram0_set_prot(uint32_t *split_addr, bool lw, boo
|
||||
uint32_t addr = (uint32_t)split_addr;
|
||||
|
||||
//low boundary check provided by LD script. see comment in esp_memprot_iram0_set_prot()
|
||||
assert( addr <= DRAM0_SPL_BLOCK_HIGH );
|
||||
HAL_ASSERT(addr <= DRAM0_SPL_BLOCK_HIGH);
|
||||
|
||||
//set low region
|
||||
int uni_blocks_low = -1;
|
||||
@ -615,7 +617,7 @@ static inline void esp_memprot_dram0_set_prot(uint32_t *split_addr, bool lw, boo
|
||||
|
||||
//check split address is WORD aligned
|
||||
uint32_t reg_split_addr = addr >> 2;
|
||||
assert(addr == (reg_split_addr << 2));
|
||||
HAL_ASSERT(addr == (reg_split_addr << 2));
|
||||
|
||||
//shift aligned split address to proper bit offset
|
||||
reg_split_addr = (reg_split_addr << DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR_S) & DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR_M;
|
||||
|
||||
@ -20,12 +20,12 @@
|
||||
|
||||
// The Lowlevel layer for SPI Flash Encryption.
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <string.h>
|
||||
#include "soc/system_reg.h"
|
||||
#include "soc/hwcrypto_reg.h"
|
||||
#include "soc/soc.h"
|
||||
#include "string.h"
|
||||
#include "assert.h"
|
||||
#include <stdbool.h>
|
||||
#include "hal/assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@ -67,7 +67,7 @@ static inline void spi_flash_encrypt_ll_disable(void)
|
||||
static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
|
||||
{
|
||||
// Our hardware only support flash encryption
|
||||
assert(type == FLASH_ENCRYPTION_MANU);
|
||||
HAL_ASSERT(type == FLASH_ENCRYPTION_MANU);
|
||||
REG_WRITE(AES_XTS_DESTINATION_REG, type);
|
||||
}
|
||||
|
||||
|
||||
@ -24,11 +24,12 @@
|
||||
|
||||
#include <stdlib.h> //for abs()
|
||||
#include <string.h>
|
||||
#include "hal/hal_defs.h"
|
||||
#include "esp_attr.h"
|
||||
#include "esp_types.h"
|
||||
#include "soc/spi_periph.h"
|
||||
#include "esp32s3/rom/lldesc.h"
|
||||
#include "esp_attr.h"
|
||||
#include "soc/lldesc.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/misc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@ -37,7 +38,7 @@ extern "C" {
|
||||
/// Interrupt not used. Don't use in app.
|
||||
#define SPI_LL_UNUSED_INT_MASK (SPI_TRANS_DONE_INT_ENA | SPI_SLV_WR_DMA_DONE_INT_ENA | SPI_SLV_RD_DMA_DONE_INT_ENA | SPI_SLV_WR_BUF_DONE_INT_ENA | SPI_SLV_RD_BUF_DONE_INT_ENA)
|
||||
/// Swap the bit order to its correct place to send
|
||||
#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)data<<(32-len))
|
||||
#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len))
|
||||
/// This is the expected clock frequency
|
||||
#define SPI_LL_PERIPH_CLK_FREQ (80 * 1000000)
|
||||
#define SPI_LL_GET_HW(ID) ((ID)==0? ({abort();NULL;}):((ID)==1? &GPSPI2 : &GPSPI3))
|
||||
@ -351,9 +352,9 @@ static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_s
|
||||
*/
|
||||
static inline void spi_ll_write_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t *data, int len)
|
||||
{
|
||||
assert(byte_id+len <= 64);
|
||||
assert(len > 0);
|
||||
assert(byte_id >= 0);
|
||||
HAL_ASSERT(byte_id+len <= 64);
|
||||
HAL_ASSERT(len > 0);
|
||||
HAL_ASSERT(byte_id >= 0);
|
||||
|
||||
while (len > 0) {
|
||||
uint32_t word;
|
||||
|
||||
@ -15,8 +15,8 @@
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <assert.h>
|
||||
#include "soc/systimer_struct.h"
|
||||
#include "hal/assert.h"
|
||||
|
||||
#define SYSTIMER_LL_COUNTER_CLOCK (0) // Counter used for "wallclock" time
|
||||
#define SYSTIMER_LL_COUNTER_OS_TICK (1) // Counter used for OS tick
|
||||
@ -121,7 +121,7 @@ __attribute__((always_inline)) static inline void systimer_ll_enable_alarm_perio
|
||||
|
||||
__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(systimer_dev_t *dev, uint32_t alarm_id, uint32_t period)
|
||||
{
|
||||
assert(period < (1 << 26));
|
||||
HAL_ASSERT(period < (1 << 26));
|
||||
dev->target_conf[alarm_id].target_period = period;
|
||||
}
|
||||
|
||||
|
||||
@ -22,8 +22,9 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdlib.h>
|
||||
#include "hal/timer_types.h"
|
||||
#include "soc/timer_periph.h"
|
||||
#include "hal/timer_types.h"
|
||||
#include "hal/assert.h"
|
||||
|
||||
_Static_assert(TIMER_INTR_T0 == TIMG_T0_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
|
||||
_Static_assert(TIMER_INTR_T1 == TIMG_T1_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
|
||||
@ -48,7 +49,7 @@ typedef struct {
|
||||
*/
|
||||
static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t divider)
|
||||
{
|
||||
assert(divider >= 2 && divider <= 65536);
|
||||
HAL_ASSERT(divider >= 2 && divider <= 65536);
|
||||
if (divider >= 65536) {
|
||||
divider = 0;
|
||||
}
|
||||
|
||||
@ -28,6 +28,7 @@ extern "C" {
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "hal/misc.h"
|
||||
#include "hal/twai_types.h"
|
||||
#include "soc/twai_periph.h"
|
||||
|
||||
@ -482,8 +483,8 @@ static inline void twai_ll_set_tec(twai_dev_t *hw, uint32_t tec)
|
||||
*/
|
||||
static inline void twai_ll_set_acc_filter(twai_dev_t* hw, uint32_t code, uint32_t mask, bool single_filter)
|
||||
{
|
||||
uint32_t code_swapped = __builtin_bswap32(code);
|
||||
uint32_t mask_swapped = __builtin_bswap32(mask);
|
||||
uint32_t code_swapped = HAL_SWAP32(code);
|
||||
uint32_t mask_swapped = HAL_SWAP32(mask);
|
||||
for (int i = 0; i < 4; i++) {
|
||||
hw->acceptance_filter.acr[i].byte = ((code_swapped >> (i * 8)) & 0xFF);
|
||||
hw->acceptance_filter.amr[i].byte = ((mask_swapped >> (i * 8)) & 0xFF);
|
||||
@ -555,12 +556,12 @@ static inline void twai_ll_format_frame_buffer(uint32_t id, uint8_t dlc, const u
|
||||
|
||||
//Set ID. The ID registers are big endian and left aligned, therefore a bswap will be required
|
||||
if (is_extd) {
|
||||
uint32_t id_temp = __builtin_bswap32((id & TWAI_EXTD_ID_MASK) << 3); //((id << 3) >> 8*(3-i))
|
||||
uint32_t id_temp = HAL_SWAP32((id & TWAI_EXTD_ID_MASK) << 3); //((id << 3) >> 8*(3-i))
|
||||
for (int i = 0; i < 4; i++) {
|
||||
tx_frame->extended.id[i] = (id_temp >> (8 * i)) & 0xFF;
|
||||
}
|
||||
} else {
|
||||
uint32_t id_temp = __builtin_bswap16((id & TWAI_STD_ID_MASK) << 5); //((id << 5) >> 8*(1-i))
|
||||
uint32_t id_temp = HAL_SWAP16((id & TWAI_STD_ID_MASK) << 5); //((id << 5) >> 8*(1-i))
|
||||
for (int i = 0; i < 2; i++) {
|
||||
tx_frame->standard.id[i] = (id_temp >> (8 * i)) & 0xFF;
|
||||
}
|
||||
@ -600,14 +601,14 @@ static inline void twai_ll_prase_frame_buffer(twai_ll_frame_buffer_t *rx_frame,
|
||||
for (int i = 0; i < 4; i++) {
|
||||
id_temp |= rx_frame->extended.id[i] << (8 * i);
|
||||
}
|
||||
id_temp = __builtin_bswap32(id_temp) >> 3; //((byte[i] << 8*(3-i)) >> 3)
|
||||
id_temp = HAL_SWAP32(id_temp) >> 3; //((byte[i] << 8*(3-i)) >> 3)
|
||||
*id = id_temp & TWAI_EXTD_ID_MASK;
|
||||
} else {
|
||||
uint32_t id_temp = 0;
|
||||
for (int i = 0; i < 2; i++) {
|
||||
id_temp |= rx_frame->standard.id[i] << (8 * i);
|
||||
}
|
||||
id_temp = __builtin_bswap16(id_temp) >> 5; //((byte[i] << 8*(1-i)) >> 5)
|
||||
id_temp = HAL_SWAP16(id_temp) >> 5; //((byte[i] << 8*(1-i)) >> 5)
|
||||
*id = id_temp & TWAI_STD_ID_MASK;
|
||||
}
|
||||
|
||||
|
||||
@ -21,8 +21,6 @@
|
||||
#pragma once
|
||||
|
||||
#include "hal/dac_ll.h"
|
||||
#include "hal/hal_defs.h"
|
||||
#include <esp_err.h>
|
||||
|
||||
/**
|
||||
* Power on dac module and start output voltage.
|
||||
|
||||
@ -29,6 +29,7 @@ NOTE: Thread safety is the responsibility fo the HAL user. All USB Host HAL
|
||||
#include "soc/usb_wrap_struct.h"
|
||||
#include "hal/usbh_ll.h"
|
||||
#include "hal/usb_types_private.h"
|
||||
#include "hal/assert.h"
|
||||
|
||||
// ------------------------------------------------ Macros and Types ---------------------------------------------------
|
||||
|
||||
@ -322,7 +323,7 @@ static inline void usbh_hal_port_toggle_power(usbh_hal_context_t *hal, bool powe
|
||||
*/
|
||||
static inline void usbh_hal_port_toggle_reset(usbh_hal_context_t *hal, bool enable)
|
||||
{
|
||||
assert(hal->channels.num_allocd == 0); //Cannot reset if there are still allocated channels
|
||||
HAL_ASSERT(hal->channels.num_allocd == 0); //Cannot reset if there are still allocated channels
|
||||
usbh_ll_hprt_set_port_reset(hal->dev, enable);
|
||||
}
|
||||
|
||||
@ -410,7 +411,7 @@ static inline bool usbh_hal_port_check_resume(usbh_hal_context_t *hal)
|
||||
*/
|
||||
static inline void usbh_hal_port_set_frame_list(usbh_hal_context_t *hal, uint32_t *frame_list, usb_hal_frame_list_len_t len)
|
||||
{
|
||||
assert(!hal->flags.periodic_sched_enabled);
|
||||
HAL_ASSERT(!hal->flags.periodic_sched_enabled);
|
||||
//Clear and save frame list
|
||||
hal->periodic_frame_list = frame_list;
|
||||
hal->frame_list_len = len;
|
||||
@ -438,7 +439,7 @@ static inline uint32_t *usbh_hal_port_get_frame_list(usbh_hal_context_t *hal)
|
||||
*/
|
||||
static inline void usbh_hal_port_periodic_enable(usbh_hal_context_t *hal)
|
||||
{
|
||||
assert(hal->periodic_frame_list != NULL);
|
||||
HAL_ASSERT(hal->periodic_frame_list != NULL);
|
||||
usbh_ll_set_frame_list_base_addr(hal->dev, (uint32_t)hal->periodic_frame_list);
|
||||
usbh_ll_hcfg_set_num_frame_list_entries(hal->dev, hal->frame_list_len);
|
||||
usbh_ll_hcfg_en_perio_sched(hal->dev);
|
||||
@ -458,7 +459,7 @@ static inline void usbh_hal_port_periodic_enable(usbh_hal_context_t *hal)
|
||||
*/
|
||||
static inline void usbh_hal_port_periodic_disable(usbh_hal_context_t *hal)
|
||||
{
|
||||
assert(hal->flags.periodic_sched_enabled);
|
||||
HAL_ASSERT(hal->flags.periodic_sched_enabled);
|
||||
usbh_ll_hcfg_dis_perio_sched(hal->dev);
|
||||
hal->flags.periodic_sched_enabled = 0;
|
||||
}
|
||||
@ -602,7 +603,7 @@ void usbh_hal_chan_set_ep_char(usbh_hal_context_t *hal, usbh_hal_chan_t *chan_ob
|
||||
static inline void usbh_hal_chan_set_dir(usbh_hal_chan_t *chan_obj, bool is_in)
|
||||
{
|
||||
//Cannot change direction whilst channel is still active or in error
|
||||
assert(!chan_obj->flags.active && !chan_obj->flags.error_pending);
|
||||
HAL_ASSERT(!chan_obj->flags.active && !chan_obj->flags.error_pending);
|
||||
usbh_ll_chan_set_dir(chan_obj->regs, is_in);
|
||||
}
|
||||
|
||||
@ -621,7 +622,7 @@ static inline void usbh_hal_chan_set_dir(usbh_hal_chan_t *chan_obj, bool is_in)
|
||||
static inline void usbh_hal_chan_set_pid(usbh_hal_chan_t *chan_obj, int pid)
|
||||
{
|
||||
//Cannot change pid whilst channel is still active or in error
|
||||
assert(!chan_obj->flags.active && !chan_obj->flags.error_pending);
|
||||
HAL_ASSERT(!chan_obj->flags.active && !chan_obj->flags.error_pending);
|
||||
//Update channel object and set the register
|
||||
usbh_ll_chan_set_pid(chan_obj->regs, pid);
|
||||
}
|
||||
@ -638,7 +639,7 @@ static inline void usbh_hal_chan_set_pid(usbh_hal_chan_t *chan_obj, int pid)
|
||||
*/
|
||||
static inline uint32_t usbh_hal_chan_get_pid(usbh_hal_chan_t *chan_obj)
|
||||
{
|
||||
assert(!chan_obj->flags.active && !chan_obj->flags.error_pending);
|
||||
HAL_ASSERT(!chan_obj->flags.active && !chan_obj->flags.error_pending);
|
||||
return usbh_ll_chan_get_pid(chan_obj->regs);
|
||||
}
|
||||
|
||||
@ -695,7 +696,7 @@ bool usbh_hal_chan_request_halt(usbh_hal_chan_t *chan_obj);
|
||||
*/
|
||||
static inline usbh_hal_chan_error_t usbh_hal_chan_get_error(usbh_hal_chan_t *chan_obj)
|
||||
{
|
||||
assert(chan_obj->flags.error_pending);
|
||||
HAL_ASSERT(chan_obj->flags.error_pending);
|
||||
return chan_obj->error;
|
||||
}
|
||||
|
||||
@ -707,7 +708,7 @@ static inline usbh_hal_chan_error_t usbh_hal_chan_get_error(usbh_hal_chan_t *cha
|
||||
static inline void usbh_hal_chan_clear_error(usbh_hal_chan_t *chan_obj)
|
||||
{
|
||||
//Can only clear error when an error has occurred
|
||||
assert(chan_obj->flags.error_pending);
|
||||
HAL_ASSERT(chan_obj->flags.error_pending);
|
||||
chan_obj->flags.error_pending = 0;
|
||||
}
|
||||
|
||||
|
||||
43
components/hal/platform_port/include/hal/assert.h
Normal file
43
components/hal/platform_port/include/hal/assert.h
Normal file
@ -0,0 +1,43 @@
|
||||
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#include "sdkconfig.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern void __assert_func(const char *file, int line, const char *func, const char *expr);
|
||||
extern void abort(void);
|
||||
|
||||
#ifndef __ASSERT_FUNC
|
||||
#ifdef __ASSERT_FUNCTION
|
||||
#define __ASSERT_FUNC __ASSERT_FUNCTION
|
||||
#else
|
||||
#define __ASSERT_FUNC "??"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if CONFIG_HAL_DEFAULT_ASSERTION_LEVEL == 1 // silent
|
||||
#define HAL_ASSERT(__e) (__builtin_expect(!!(__e), 1) ? (void)0 : abort())
|
||||
#elif CONFIG_HAL_DEFAULT_ASSERTION_LEVEL == 2 // full assertion
|
||||
#define HAL_ASSERT(__e) (__builtin_expect(!!(__e), 1) ? (void)0 : __assert_func(__FILE__, __LINE__, __ASSERT_FUNC, #__e))
|
||||
#else // no assert
|
||||
#define HAL_ASSERT(__e) ((void)(__e))
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
17
components/hal/platform_port/include/hal/check.h
Normal file
17
components/hal/platform_port/include/hal/check.h
Normal file
@ -0,0 +1,17 @@
|
||||
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#define STATIC_HAL_REG_CHECK(TAG, ENUM, VAL) _Static_assert((ENUM) == (VAL), #TAG": "#ENUM" definition no longer matches register value")
|
||||
@ -1,9 +1,9 @@
|
||||
// Copyright 2010-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
@ -16,15 +16,8 @@
|
||||
|
||||
#include "esp_log.h"
|
||||
|
||||
// platform related stuff
|
||||
|
||||
#define HAL_SWAP32(word) __builtin_bswap32(word)
|
||||
#define HAL_SWAP64(word) __builtin_bswap64(word)
|
||||
|
||||
#define HAL_LOGE(...) ESP_LOGE(__VA_ARGS__)
|
||||
#define HAL_LOGW(...) ESP_LOGW(__VA_ARGS__)
|
||||
#define HAL_LOGI(...) ESP_LOGI(__VA_ARGS__)
|
||||
#define HAL_LOGD(...) ESP_LOGD(__VA_ARGS__)
|
||||
#define HAL_LOGV(...) ESP_LOGV(__VA_ARGS__)
|
||||
|
||||
#define STATIC_HAL_REG_CHECK(TAG, ENUM, VAL) _Static_assert((ENUM) == (VAL), #TAG" "#ENUM" definition no longer matches register value")
|
||||
18
components/hal/platform_port/include/hal/misc.h
Normal file
18
components/hal/platform_port/include/hal/misc.h
Normal file
@ -0,0 +1,18 @@
|
||||
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#define HAL_SWAP16(d) __builtin_bswap16((d))
|
||||
#define HAL_SWAP32(d) __builtin_bswap32((d))
|
||||
#define HAL_SWAP64(d) __builtin_bswap64((d))
|
||||
@ -14,13 +14,14 @@
|
||||
|
||||
// The HAL layer for SDIO slave (common part)
|
||||
|
||||
#include <soc/slc_struct.h>
|
||||
#include <soc/hinf_struct.h>
|
||||
#include <hal/sdio_slave_types.h>
|
||||
#include <soc/host_struct.h>
|
||||
#include <string.h>
|
||||
#include "soc/slc_struct.h"
|
||||
#include "soc/hinf_struct.h"
|
||||
#include "hal/sdio_slave_types.h"
|
||||
#include "soc/host_struct.h"
|
||||
#include "hal/sdio_slave_hal.h"
|
||||
#include "hal/hal_defs.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/log.h"
|
||||
#include "esp_attr.h"
|
||||
|
||||
|
||||
@ -103,7 +104,7 @@ static esp_err_t sdio_ringbuf_send(sdio_ringbuf_t *buf, esp_err_t (*copy_callbac
|
||||
// since this is designed to be called in the ISR, no parallel logic
|
||||
static inline esp_err_t sdio_ringbuf_recv(sdio_ringbuf_t *buf, uint8_t **start, uint8_t **end, ringbuf_get_all_t get_all)
|
||||
{
|
||||
assert(buf->free_ptr == buf->read_ptr); //must return before recv again
|
||||
HAL_ASSERT(buf->free_ptr == buf->read_ptr); //must return before recv again
|
||||
if (start == NULL && end == NULL) return ESP_ERR_INVALID_ARG; // must have a output
|
||||
if (buf->read_ptr == buf->write_ptr) return ESP_ERR_NOT_FOUND; // no data
|
||||
|
||||
@ -126,10 +127,10 @@ static inline esp_err_t sdio_ringbuf_recv(sdio_ringbuf_t *buf, uint8_t **start,
|
||||
|
||||
static inline int sdio_ringbuf_return(sdio_ringbuf_t* buf, uint8_t *ptr)
|
||||
{
|
||||
assert(sdio_ringbuf_offset_ptr(buf, RINGBUF_FREE_PTR, SDIO_SLAVE_SEND_DESC_SIZE) == ptr);
|
||||
HAL_ASSERT(sdio_ringbuf_offset_ptr(buf, RINGBUF_FREE_PTR, SDIO_SLAVE_SEND_DESC_SIZE) == ptr);
|
||||
size_t size = (buf->read_ptr + buf->size - buf->free_ptr) % buf->size;
|
||||
size_t count = size / SDIO_SLAVE_SEND_DESC_SIZE;
|
||||
assert(count * SDIO_SLAVE_SEND_DESC_SIZE==size);
|
||||
HAL_ASSERT(count * SDIO_SLAVE_SEND_DESC_SIZE==size);
|
||||
buf->free_ptr = buf->read_ptr;
|
||||
return count;
|
||||
}
|
||||
@ -208,7 +209,7 @@ static esp_err_t init_send_queue(sdio_slave_context_t *hal)
|
||||
//clear the queue
|
||||
rcv_res = sdio_ringbuf_recv(buf, (uint8_t **) &first, (uint8_t **) &last, RINGBUF_GET_ALL);
|
||||
assert (rcv_res == ESP_OK);
|
||||
assert(first == last); //there should be only one desc remain
|
||||
HAL_ASSERT(first == last); //there should be only one desc remain
|
||||
sdio_ringbuf_return(buf, (uint8_t *) first);
|
||||
return ESP_OK;
|
||||
}
|
||||
@ -316,7 +317,7 @@ static void send_new_packet(sdio_slave_context_t *hal)
|
||||
// and restart new link list operation
|
||||
sdio_slave_hal_send_desc_t *const start_desc = hal->in_flight_head;
|
||||
sdio_slave_hal_send_desc_t *const end_desc = hal->in_flight_end;
|
||||
assert(start_desc != NULL && end_desc != NULL);
|
||||
HAL_ASSERT(start_desc != NULL && end_desc != NULL);
|
||||
|
||||
sdio_slave_ll_send_stop(hal->slc);
|
||||
sdio_slave_ll_send_reset(hal->slc);
|
||||
@ -358,7 +359,7 @@ bool sdio_slave_hal_send_eof_happened(sdio_slave_context_t* hal)
|
||||
// also update sequence and recycle descs.
|
||||
if (sdio_slave_ll_send_done(hal->slc)) {
|
||||
//check current state
|
||||
assert(send_get_state(hal) == STATE_SENDING);
|
||||
HAL_ASSERT(send_get_state(hal) == STATE_SENDING);
|
||||
sdio_slave_ll_send_intr_clr(hal->slc);
|
||||
return true;
|
||||
} else {
|
||||
@ -399,7 +400,7 @@ static esp_err_t send_get_inflight_desc(sdio_slave_context_t *hal, void **out_ar
|
||||
{
|
||||
esp_err_t ret;
|
||||
if (init) {
|
||||
assert(hal->returned_desc == NULL);
|
||||
HAL_ASSERT(hal->returned_desc == NULL);
|
||||
hal->returned_desc = hal->in_flight_head;
|
||||
send_set_state(hal, STATE_GETTING_RESULT);
|
||||
}
|
||||
@ -411,7 +412,7 @@ static esp_err_t send_get_inflight_desc(sdio_slave_context_t *hal, void **out_ar
|
||||
} else {
|
||||
if (hal->in_flight_head != NULL) {
|
||||
// fix the link broken of last desc when being sent
|
||||
assert(hal->in_flight_end != NULL);
|
||||
HAL_ASSERT(hal->in_flight_end != NULL);
|
||||
SEND_DESC_NEXT_SET(hal->in_flight_end, hal->in_flight_next);
|
||||
|
||||
*out_returned_cnt = sdio_ringbuf_return(&(hal->send_desc_queue), (uint8_t*)hal->in_flight_head);
|
||||
@ -433,7 +434,7 @@ static esp_err_t send_get_unsent_desc(sdio_slave_context_t *hal, void **out_arg,
|
||||
|
||||
if (ret == ESP_OK) {
|
||||
//currently each packet takes only one desc.
|
||||
assert(head == tail);
|
||||
HAL_ASSERT(head == tail);
|
||||
(*out_arg) = head->arg;
|
||||
(*out_return_cnt) = sdio_ringbuf_return(&(hal->send_desc_queue), (uint8_t*) head);
|
||||
} else if (ret == ESP_ERR_NOT_FOUND) {
|
||||
@ -450,9 +451,9 @@ esp_err_t sdio_slave_hal_send_get_next_finished_arg(sdio_slave_context_t *hal, v
|
||||
{
|
||||
bool init = (send_get_state(hal) == STATE_SENDING);
|
||||
if (init) {
|
||||
assert(hal->in_flight_head != NULL);
|
||||
HAL_ASSERT(hal->in_flight_head != NULL);
|
||||
} else {
|
||||
assert(send_get_state(hal) == STATE_GETTING_RESULT);
|
||||
HAL_ASSERT(send_get_state(hal) == STATE_GETTING_RESULT);
|
||||
}
|
||||
*out_returned_cnt = 0;
|
||||
|
||||
|
||||
@ -16,10 +16,10 @@
|
||||
// The IRAM part is in spi_flash_hal_iram.c, spi_flash_hal_gpspi.c, spi_flash_hal_common.inc.
|
||||
|
||||
#include <stdlib.h>
|
||||
#include "hal/spi_flash_hal.h"
|
||||
#include "string.h"
|
||||
#include <string.h>
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/hal_defs.h"
|
||||
#include "hal/spi_flash_hal.h"
|
||||
#include "hal/log.h"
|
||||
|
||||
#define APB_CYCLE_NS (1000*1000*1000LL/APB_CLK_FREQ)
|
||||
|
||||
@ -97,7 +97,7 @@ esp_err_t spi_flash_hal_init(spi_flash_hal_context_t *data_out, const spi_flash_
|
||||
data_out->flags |= SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_RESUME;
|
||||
}
|
||||
|
||||
ESP_EARLY_LOGD(TAG, "extra_dummy: %d", data_out->extra_dummy);
|
||||
HAL_LOGD(TAG, "extra_dummy: %d", data_out->extra_dummy);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
|
||||
@ -12,10 +12,10 @@
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
#include "hal/spi_flash_hal.h"
|
||||
#include "string.h"
|
||||
#include "hal/hal_defs.h"
|
||||
#include "hal/assert.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "sdkconfig.h"
|
||||
|
||||
@ -106,7 +106,7 @@ esp_err_t spi_flash_hal_configure_host_io_mode(
|
||||
*/
|
||||
int m70_bits = addr_bitlen - 24;
|
||||
if (m70_bits) {
|
||||
assert(io_mode == SPI_FLASH_DIO || io_mode == SPI_FLASH_QIO);
|
||||
HAL_ASSERT(io_mode == SPI_FLASH_DIO || io_mode == SPI_FLASH_QIO);
|
||||
conf_required = true;
|
||||
addr_bitlen -= m70_bits;
|
||||
int line_width = (io_mode == SPI_FLASH_DIO? 2: 4);
|
||||
|
||||
@ -15,6 +15,7 @@
|
||||
// The HAL layer for SPI (common part)
|
||||
|
||||
#include "hal/spi_hal.h"
|
||||
#include "hal/log.h"
|
||||
#include "soc/soc_caps.h"
|
||||
|
||||
//This GDMA related part will be introduced by GDMA dedicated APIs in the future. Here we temporarily use macros.
|
||||
|
||||
@ -16,6 +16,7 @@
|
||||
// make these functions in a seperate file to make sure all LL functions are in the IRAM.
|
||||
|
||||
#include "hal/spi_hal.h"
|
||||
#include "hal/assert.h"
|
||||
#include "soc/soc_caps.h"
|
||||
|
||||
//This GDMA related part will be introduced by GDMA dedicated APIs in the future. Here we temporarily use macros.
|
||||
@ -64,7 +65,7 @@ void spi_hal_setup_trans(spi_hal_context_t *hal, const spi_hal_dev_config_t *dev
|
||||
//clear int bit
|
||||
spi_ll_clear_int_stat(hal->hw);
|
||||
//We should be done with the transmission.
|
||||
assert(spi_ll_get_running_cmd(hw) == 0);
|
||||
HAL_ASSERT(spi_ll_get_running_cmd(hw) == 0);
|
||||
|
||||
spi_ll_master_set_io_mode(hw, trans->io_mode);
|
||||
|
||||
|
||||
@ -21,8 +21,9 @@
|
||||
#include "sdkconfig.h"
|
||||
#include "soc/spi_periph.h"
|
||||
#include "soc/lldesc.h"
|
||||
#include "hal/spi_slave_hd_hal.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/spi_slave_hd_hal.h"
|
||||
#include "hal/assert.h"
|
||||
|
||||
//This GDMA related part will be introduced by GDMA dedicated APIs in the future. Here we temporarily use macros.
|
||||
#if SOC_GDMA_SUPPORTED
|
||||
@ -297,7 +298,7 @@ bool spi_slave_hd_hal_get_rx_finished_trans(spi_slave_hd_hal_context_t *hal, voi
|
||||
//Append mode is only supported on ESP32S2 now
|
||||
static void spi_slave_hd_hal_link_append_desc(spi_slave_hd_hal_desc_append_t *dmadesc, const void *data, int len, bool isrx, void *arg)
|
||||
{
|
||||
assert(len <= LLDESC_MAX_NUM_PER_DESC); //TODO: Add support for transaction with length larger than 4092, IDF-2660
|
||||
HAL_ASSERT(len <= LLDESC_MAX_NUM_PER_DESC); //TODO: Add support for transaction with length larger than 4092, IDF-2660
|
||||
int n = 0;
|
||||
while (len) {
|
||||
int dmachunklen = len;
|
||||
|
||||
@ -18,6 +18,7 @@
|
||||
#include "hal/systimer_ll.h"
|
||||
#include "hal/systimer_types.h"
|
||||
#include "hal/clk_gate_ll.h"
|
||||
#include "hal/assert.h"
|
||||
|
||||
void systimer_hal_init(systimer_hal_context_t *hal)
|
||||
{
|
||||
@ -174,7 +175,7 @@ void systimer_hal_on_apb_freq_update(systimer_hal_context_t *hal, uint32_t apb_t
|
||||
* XTAL_STEP value accordingly.
|
||||
*/
|
||||
if (apb_ticks_per_us != SYSTIMER_LL_TICKS_PER_US) {
|
||||
assert((SYSTIMER_LL_TICKS_PER_US % apb_ticks_per_us) == 0 && "TICK_PER_US should be divisible by APB frequency (in MHz)");
|
||||
HAL_ASSERT((SYSTIMER_LL_TICKS_PER_US % apb_ticks_per_us) == 0 && "TICK_PER_US should be divisible by APB frequency (in MHz)");
|
||||
systimer_ll_set_step_for_xtal(hal->dev, SYSTIMER_LL_TICKS_PER_US / apb_ticks_per_us);
|
||||
}
|
||||
}
|
||||
|
||||
@ -14,11 +14,11 @@
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
#include <string.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "hal/usbh_hal.h"
|
||||
#include "hal/usbh_ll.h"
|
||||
#include "hal/assert.h"
|
||||
|
||||
// ------------------------------------------------ Macros and Types ---------------------------------------------------
|
||||
|
||||
@ -117,7 +117,7 @@ void usbh_hal_init(usbh_hal_context_t *hal)
|
||||
//Check if a peripheral is alive by reading the core ID registers
|
||||
usbh_dev_t *dev = &USBH;
|
||||
uint32_t core_id = usb_ll_get_controller_core_id(dev);
|
||||
assert(core_id == CORE_REG_GSNPSID);
|
||||
HAL_ASSERT(core_id == CORE_REG_GSNPSID);
|
||||
(void) core_id; //Suppress unused variable warning if asserts are disabled
|
||||
//Initialize HAL context
|
||||
memset(hal, 0, sizeof(usbh_hal_context_t));
|
||||
@ -157,11 +157,11 @@ void usbh_hal_core_soft_reset(usbh_hal_context_t *hal)
|
||||
|
||||
void usbh_hal_set_fifo_size(usbh_hal_context_t *hal, const usbh_hal_fifo_config_t *fifo_config)
|
||||
{
|
||||
assert((fifo_config->rx_fifo_lines + fifo_config->nptx_fifo_lines + fifo_config->ptx_fifo_lines) <= USBH_HAL_FIFO_TOTAL_USABLE_LINES);
|
||||
HAL_ASSERT((fifo_config->rx_fifo_lines + fifo_config->nptx_fifo_lines + fifo_config->ptx_fifo_lines) <= USBH_HAL_FIFO_TOTAL_USABLE_LINES);
|
||||
//Check that none of the channels are active
|
||||
for (int i = 0; i < USBH_HAL_NUM_CHAN; i++) {
|
||||
if (hal->channels.hdls[i] != NULL) {
|
||||
assert(!hal->channels.hdls[i]->flags.active);
|
||||
HAL_ASSERT(!hal->channels.hdls[i]->flags.active);
|
||||
}
|
||||
}
|
||||
//Set the new FIFO lengths
|
||||
@ -199,7 +199,7 @@ void usbh_hal_port_enable(usbh_hal_context_t *hal)
|
||||
|
||||
bool usbh_hal_chan_alloc(usbh_hal_context_t *hal, usbh_hal_chan_t *chan_obj, void *chan_ctx)
|
||||
{
|
||||
assert(hal->flags.fifo_sizes_set); //FIFO sizes should be set befor attempting to allocate a channel
|
||||
HAL_ASSERT(hal->flags.fifo_sizes_set); //FIFO sizes should be set befor attempting to allocate a channel
|
||||
//Attempt to allocate channel
|
||||
if (hal->channels.num_allocd == USBH_HAL_NUM_CHAN) {
|
||||
return false; //Out of free channels
|
||||
@ -213,7 +213,7 @@ bool usbh_hal_chan_alloc(usbh_hal_context_t *hal, usbh_hal_chan_t *chan_obj, voi
|
||||
break;
|
||||
}
|
||||
}
|
||||
assert(chan_idx != -1);
|
||||
HAL_ASSERT(chan_idx != -1);
|
||||
//Initialize channel object
|
||||
memset(chan_obj, 0, sizeof(usbh_hal_chan_t));
|
||||
chan_obj->flags.chan_idx = chan_idx;
|
||||
@ -238,13 +238,13 @@ void usbh_hal_chan_free(usbh_hal_context_t *hal, usbh_hal_chan_t *chan_obj)
|
||||
}
|
||||
}
|
||||
//Can only free a channel when in the disabled state and descriptor list released
|
||||
assert(!chan_obj->flags.active && !chan_obj->flags.error_pending);
|
||||
HAL_ASSERT(!chan_obj->flags.active && !chan_obj->flags.error_pending);
|
||||
//Disable channel's interrupt
|
||||
usbh_ll_haintmsk_dis_chan_intr(hal->dev, 1 << chan_obj->flags.chan_idx);
|
||||
//Deallocate channel
|
||||
hal->channels.hdls[chan_obj->flags.chan_idx] = NULL;
|
||||
hal->channels.num_allocd--;
|
||||
assert(hal->channels.num_allocd >= 0);
|
||||
HAL_ASSERT(hal->channels.num_allocd >= 0);
|
||||
}
|
||||
|
||||
// ---------------- Channel Configuration ------------------
|
||||
@ -252,7 +252,7 @@ void usbh_hal_chan_free(usbh_hal_context_t *hal, usbh_hal_chan_t *chan_obj)
|
||||
void usbh_hal_chan_set_ep_char(usbh_hal_context_t *hal, usbh_hal_chan_t *chan_obj, usbh_hal_ep_char_t *ep_char)
|
||||
{
|
||||
//Cannot change ep_char whilst channel is still active or in error
|
||||
assert(!chan_obj->flags.active && !chan_obj->flags.error_pending);
|
||||
HAL_ASSERT(!chan_obj->flags.active && !chan_obj->flags.error_pending);
|
||||
//Set the endpoint characteristics of the pipe
|
||||
usbh_ll_chan_hcchar_init(chan_obj->regs,
|
||||
ep_char->dev_addr,
|
||||
@ -265,7 +265,7 @@ void usbh_hal_chan_set_ep_char(usbh_hal_context_t *hal, usbh_hal_chan_t *chan_ob
|
||||
chan_obj->type = ep_char->type;
|
||||
//If this is a periodic endpoint/channel, set its schedule in the frame list
|
||||
if (ep_char->type == USB_PRIV_XFER_TYPE_ISOCHRONOUS || ep_char->type == USB_PRIV_XFER_TYPE_INTR) {
|
||||
assert((int)ep_char->periodic.interval <= (int)hal->frame_list_len); //Interval cannot exceed the length of the frame list
|
||||
HAL_ASSERT((int)ep_char->periodic.interval <= (int)hal->frame_list_len); //Interval cannot exceed the length of the frame list
|
||||
//Find the effective offset in the frame list (in case the phase_offset_frames > interval)
|
||||
int offset = ep_char->periodic.phase_offset_frames % ep_char->periodic.interval;
|
||||
//Schedule the channel in the frame list
|
||||
@ -280,7 +280,7 @@ void usbh_hal_chan_set_ep_char(usbh_hal_context_t *hal, usbh_hal_chan_t *chan_ob
|
||||
void usbh_hal_chan_activate(usbh_hal_chan_t *chan_obj, void *xfer_desc_list, int desc_list_len, int start_idx)
|
||||
{
|
||||
//Cannot activate a channel that has already been enabled or is pending error handling
|
||||
assert(!chan_obj->flags.active && !chan_obj->flags.error_pending);
|
||||
HAL_ASSERT(!chan_obj->flags.active && !chan_obj->flags.error_pending);
|
||||
//Set start address of the QTD list and starting QTD index
|
||||
usbh_ll_chan_set_dma_addr_non_iso(chan_obj->regs, xfer_desc_list, start_idx);
|
||||
usbh_ll_chan_set_qtd_list_len(chan_obj->regs, desc_list_len);
|
||||
@ -291,7 +291,7 @@ void usbh_hal_chan_activate(usbh_hal_chan_t *chan_obj, void *xfer_desc_list, int
|
||||
bool usbh_hal_chan_request_halt(usbh_hal_chan_t *chan_obj)
|
||||
{
|
||||
//Cannot request halt on a channel that is pending error handling
|
||||
assert(!chan_obj->flags.error_pending);
|
||||
HAL_ASSERT(!chan_obj->flags.error_pending);
|
||||
if (usbh_ll_chan_is_active(chan_obj->regs) || chan_obj->flags.active) {
|
||||
usbh_ll_chan_halt(chan_obj->regs);
|
||||
chan_obj->flags.halt_requested = 1;
|
||||
@ -379,7 +379,7 @@ usbh_hal_chan_event_t usbh_hal_chan_decode_intr(usbh_hal_chan_t *chan_obj)
|
||||
usbh_hal_chan_event_t chan_event;
|
||||
|
||||
if (chan_intrs & CHAN_INTRS_ERROR_MSK) { //Note: Errors are uncommon, so we check against the entire interrupt mask to reduce frequency of entering this call path
|
||||
assert(chan_intrs & USBH_LL_INTR_CHAN_CHHLTD); //An error should have halted the channel
|
||||
HAL_ASSERT(chan_intrs & USBH_LL_INTR_CHAN_CHHLTD); //An error should have halted the channel
|
||||
//Store the error in hal context
|
||||
usbh_hal_chan_error_t error;
|
||||
if (chan_intrs & USBH_LL_INTR_CHAN_STALL) {
|
||||
|
||||
@ -33,7 +33,7 @@
|
||||
|
||||
#if defined(NDEBUG)
|
||||
|
||||
# define assert(__e) ((void)0)
|
||||
# define assert(__e) ((void)(__e))
|
||||
|
||||
#elif CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT
|
||||
|
||||
|
||||
@ -134,6 +134,7 @@ The following options will reduce IRAM usage of some ESP-IDF features:
|
||||
:esp32: - :ref:`CONFIG_SPI_FLASH_ROM_DRIVER_PATCH` disabling this option will free some IRAM but is only available in some flash configurations (see the configuration item help text).
|
||||
- Disabling :ref:`CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR` prevents posting ``esp_event`` events from :ref:`iram-safe-interrupt-handlers` but will save some IRAM.
|
||||
- Disabling :ref:`CONFIG_SPI_MASTER_ISR_IN_IRAM` prevents spi_master interrupts from being serviced while writing to flash, and may otherwise reduce spi_master performance, but will save some IRAM.
|
||||
- Setting :ref:`CONFIG_HAL_DEFAULT_ASSERTION_LEVEL` to disable assertion for HAL component will save some IRAM especially for HAL code who calls `HAL_ASSERT` a lot and resides in IRAM.
|
||||
|
||||
.. note::
|
||||
|
||||
|
||||
@ -291,6 +291,7 @@ The following configuration options will reduce the final binary size of almost
|
||||
- Set :ref:`CONFIG_COMPILER_OPTIMIZATION` to "Optimize for size (-Os)". In some cases, "Optimize for performance (-O2)" will also reduce the binary size compared to the default. Note that if your code contains C or C++ Undefined Behaviour then increasing the compiler optimization level may expose bugs that otherwise don't happen.
|
||||
- Reduce the compiled-in log output by lowering the app :ref:`CONFIG_LOG_DEFAULT_LEVEL`. If the :ref:`CONFIG_LOG_MAXIMUM_LEVEL` is changed from the default then this setting controls the binary size instead. Reducing compiled-in logging reduces the number of strings in the binary, and also the code size of the calls to logging functions.
|
||||
- Set the :ref:`CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL` to "Silent". This avoids compiling in a dedicated assertion string and source file name for each assert that may fail. It's still possible to find the failed assert in the code by looking at the memory address where the assertion failed.
|
||||
- Besides the :ref:`CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL`, you can disable or silent the assertion for HAL component separately by setting :ref:`CONFIG_HAL_DEFAULT_ASSERTION_LEVEL`.
|
||||
- Set :ref:`CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT`. This removes specific error messages for particular internal ESP-IDF error check macros. This may make it harder to debug some error conditions by reading the log output.
|
||||
:esp32: - If the binary needs to run on only certain revision(s) of ESP32, increasing :ref:`CONFIG_ESP32_REV_MIN` to match can result in a reduced binary size. This will make a large difference if setting ESP32 minimum revision 3, and PSRAM is enabled.
|
||||
:esp32c3: - If the binary needs to run on only certain revision(s) of ESP32-C3, increasing :ref:`CONFIG_ESP32C3_REV_MIN` to match can result in a reduced binary size. This is particularly true if setting ESP32-C3 minimum revision 3 and using Wi-Fi, as some functionality was moved to ROM code.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user