alex/esp-idf
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123 Commits

Author SHA1 Message Date
Sudeep Mohanty
2fc9bd61bf ulp: refactor ulp component 
This commit refactors the ulp component.
Files are now divided based on type of ulp, viz., fsm or risc-v.
Files common to both are maintained in the ulp_common folder.

This commit also adds menuconfig options for ULP within the ulp
component instead of presenting target specific configuations for ulp.
 2022-01-27 11:54:42 +05:30
Sudeep Mohanty
2ed15d8b1e ulp: Added ULP RISC-V support for esp32s3 
This commit adds support for ULP RISC-V for esp32s3.

Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
 2022-01-18 10:58:00 +05:30
Armando
9a6f894046 psram: add octal psram ECC feature 2021-12-13 20:24:52 +08:00
Armando
021e8817cf psram: make psram wrap mode unavailable 2021-12-13 20:19:32 +08:00
Roland Dobai
766aa57084 Build & config: Remove leftover files from the unsupported "make" build system 2021-11-11 15:32:36 +01:00
Alexey Gerenkov
bb9cd84cdc debug_stubs: Refactor and add support for RISCV 2021-11-04 01:33:24 +03:00
Marius Vikhammer
1cf61c849f docs: enable publishing of S3 docs 2021-09-06 09:11:17 +08:00
Marius Vikhammer
88e7b5f7be Merge branch 'feature/s3_cache_bringup' into 'master' 
soc: S3 cache bringup

Closes IDF-2952

See merge request espressif/esp-idf!12887
 2021-09-02 02:51:10 +00:00
Marius Vikhammer
bdf3a8ff29 Merge branch 'feature/xtwdt' into 'master' 
WDT: Add support for XTAL32K Watchdog timer

Closes IDF-2575

See merge request espressif/esp-idf!15000
 2021-09-02 02:44:47 +00:00
Marius Vikhammer
4869b3cd4a WDT: Add support for XTAL32K Watchdog timer 2021-09-02 09:09:00 +08:00
gaoxiaojie
191a494e08 support dcache 64Byte and 16k 2021-09-02 02:27:40 +08:00
Armando
a3dc625da6 mspi: support 120MHz Quad Flash and PSRAM on ESP32S3 2021-08-31 16:06:44 +08:00
Jiang Jiang Jian
97507ebe49 Merge branch 'feature/support_esp32s3_lightsleep' into 'master' 
support esp32s3 normal lightsleep

See merge request espressif/esp-idf!14369
 2021-07-28 15:09:37 +00:00
Li Shuai
5a3d2b1874 light sleep: modify some sleep params for esp32s3 2021-07-28 15:41:47 +08:00
SalimTerryLi
2347e68e6b
soc: move peripheral linker scripts out of target component 2021-07-22 12:55:01 +08:00
morris
2058e89448 Merge branch 'feature/fpga_bootloader' into 'master' 
Boot ESP32 & ESP32-S2 apps on FPGA

See merge request espressif/esp-idf!8270
 2021-07-18 08:06:38 +00:00
Angus Gratton
9d6366f290 esp_hw_support: Move rtc.h header from target components 2021-07-16 20:14:28 +08:00
Renz Bagaporo
b06dba7823 esp32: move app linker scripts 2021-07-16 20:14:27 +08:00
Renz Bagaporo
7c22cccb9c esp32: cleanup build script 2021-07-16 20:14:27 +08:00
Renz Bagaporo
844af01eb4 esp32: move spiram, himem 2021-07-16 20:14:26 +08:00
Renz Bagaporo
452bfda367 esp32: move dport_access 2021-07-16 20:14:26 +08:00
Renz Bagaporo
702e41e1c8 esp32s2: move crypto related functions 2021-07-16 20:14:26 +08:00
Renz Bagaporo
ea2aafbb7a esp32s2: move memprot api 2021-07-16 20:14:26 +08:00
Angus Gratton
c5d20dc231 fpga: Disable BOD when running on FPGA 2021-07-16 10:50:06 +10:00
Marius Vikhammer
126c6405f1 Merge branch 'feature/s3_default_2_config' into 'master' 
CI: add S3 default_2 unit test config

See merge request espressif/esp-idf!14279
 2021-07-15 09:29:31 +00:00
Marius Vikhammer
fe921291d2 build system: fix cxx init_priority not working on S3 2021-07-14 10:56:24 +08:00
Marius Vikhammer
5d184dcfe0 soc: update S3 memory layout 2021-07-09 12:29:56 +08:00
Marius Vikhammer
4553654f40 build system: fix rtc_data being placed in wrong region for S3 2021-07-08 18:40:01 +08:00
Ivan Grokhotkov
a6c721b24c esp32[s2,s3]: fix _flash_rodata_align value in the linker scripts 
Regression from 4702feeee. The TLS segment is located inside
.flash.rodata, so we need to get the alignment of that section, not
.flash.rodata_noload.
 2021-07-01 16:13:31 +02:00
Zhang Jun Hao
4702feeeeb esp_wifi: move unused wifi log to noload section to save binary size 2021-07-01 10:18:37 +08:00
Michael (XIAO Xufeng)
afc2bc94b3 Merge branch 'feature/add_opi_flash_psram_support' into 'master' 
spi flash: opi flash psram support and spi timing tuning  support on 727

Closes IDF-3097

See merge request espressif/esp-idf!12946
 2021-06-28 01:59:19 +00:00
Armando
bc248278f8 spiflash: add octal spi psram support on 727 2021-06-25 19:41:57 +08:00
Cao Sen Miao
f2fe0847d5 usb_serial_jtag: add initial support for S3 (including flashing, monitoring, writing, and reading) but console is not avaliable now 2021-06-18 12:42:41 +08:00
Marius Vikhammer
018582dc64 ULP: reduce max possible memory reserved for ULP coprocessor 
Some RTC slow memory is reserved by IDF, reduce CONFIG_TARGET_ULP_COPROC_RESERVE_MEM
range to reflect this.

Closes https://github.com/espressif/esp-idf/issues/7073
 2021-06-04 12:15:52 +08:00
Alex Lisitsyn
46020fe13a usb/hal/soc: initial copy of usbh support from esp32s2 
copy required usbh driver files from esp32s2
check usb host functionality using unit tests on esp32s3
 2021-06-02 17:57:50 +08:00
Ivan Grokhotkov
17c65dad27 soc: add esp32s3 sdmmc support 
* sync the latest struct header file from ESP32
* add soc_caps.h macros to distinguish between IO MUX and GPIO Matrix
  support in SDMMC on different chips.
* store GPIO matrix signal numbers in sdmmc_slot_info_t
 2021-05-10 23:21:27 +02:00
Ivan Grokhotkov
acd06daf39 Merge branch 'bugfix/spiram_h_header_guards' into 'master' 
add missing header guards to {esp32,esp32s3}/spiram.h (Github PR)

Closes IDFGH-4861

See merge request espressif/esp-idf!13435
 2021-05-06 11:49:39 +00:00
Alex Lisitsyn
ea6710ce98 soc/hal: add tinyusb support esp32s3 
add usb hal/soc, usb_ll files and esp32s3 target for usb
move usb_hal.h into soc common folder
soc/hal: fix soc and periph for usb
tinyusb: fix tinyusb io header
hal: usb_ll fix pull up/down config for esp32s3
soc/hal: fix peripheral addresses
 2021-05-06 16:20:54 +08:00
Ivan Grokhotkov
2887c88f56 spiram: add header guards to esp32s3/spiram.h and remove the exception 2021-05-05 15:27:19 +02:00
Angus Gratton
96c2acd9a8 Merge branch 'refactor/strip_systimer_hal_layer' into 'master' 
refactor HAL driver of systimer to a common systimer_hal

Closes IDF-2996

See merge request espressif/esp-idf!13027
 2021-04-23 07:45:31 +00:00
Angus Gratton
64a96ca96d Merge branch 'bugfix/RTC_CLK_CAL_CYCLES' into 'master' 
esp32xx: Fix the Number of cycles for RTC_SLOW_CLK calibration

See merge request espressif/esp-idf!13202
 2021-04-23 04:55:28 +00:00
morris
7c1e1c9e2d systimer: update soc data 2021-04-22 21:07:35 +08:00
Ivan Grokhotkov
0535195983 freertos: fix TLS run-time address calculation 
Since dd849ffc, _rodata_start label has been moved to a different
linker output section from where the TLS templates (.tdata, .tbss)
are located. Since link-time addresses of thread-local variables are
calculated relative to the section start address, this resulted in
incorrect calculation of THREADPTR/$tp registers.

Fix by introducing new linker label, _flash_rodata_start, which points
to the .flash.rodata output section where TLS variables are located,
and use it when calculating THREADPTR/$tp.

Also remove the hardcoded rodata section alignment for Xtensa targets.
Alignment of rodata can be affected by the user application, which is
the issue dd849ffc was fixing. To accommodate any possible alignment,
save it in a linker label (_flash_rodata_align) and then use when
calculating THREADPTR. Note that this is not required on RISC-V, since
this target doesn't use TPOFF.
 2021-04-21 13:45:21 +02:00
KonstantinKondrashov
8e1256ca88 esp32xx: Fix the Number of cycles for RTC_SLOW_CLK calibration 2021-04-20 06:29:42 +00:00
Omar Chebib
dd849ffc26 build: (Custom) App version info is now on a dedicated section, independent of the rodata alignment 
It is now possible to have any alignment restriction on rodata in the user
applicaiton. It will not affect the first section which must be aligned
on a 16-byte bound.

Closes https://github.com/espressif/esp-idf/issues/6719
 2021-04-19 12:53:08 +08:00
Angus Gratton
32c924b5cd esp32s3: Reserve RTC memory in bootloader in the app linker script 2021-04-15 16:20:58 +10:00
Omar Chebib
cd79f3907d gpio: Disable USB JTAG when setting pins 18 and 19 as GPIOs on ESP32C3 
When `DIS_USB_JTAG` eFuse is NOT burned (`False`), it is not possible
to set pins 18 and 19 as GPIOs. This commit solves this by manually
disabling USB JTAG when using pins 18 or 19.
The functions shall use `gpio_hal_iomux_func_sel` instead of
`PIN_FUNC_SELELECT`.
 2021-04-08 14:01:18 +08:00
Renz Bagaporo
a202a604d8 esp32: move system libs 2021-03-31 19:17:33 +08:00
Renz Bagaporo
bbc599493e esp32: move common fragment definitions 2021-03-31 19:17:33 +08:00
Renz Bagaporo
9478298aa4 esp32: move mac target specific configs 2021-03-31 19:17:33 +08:00