usb/hal/soc: initial copy of usbh support from esp32s2

copy required usbh driver files from esp32s2
check usb host functionality using unit tests on esp32s3
This commit is contained in:
Alex Lisitsyn 2021-06-02 17:57:50 +08:00 committed by Michael (XIAO Xufeng)
parent 15e0a6be90
commit 46020fe13a
10 changed files with 1184 additions and 14 deletions

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@ -37,4 +37,5 @@ PROVIDE ( DMA = 0x6003F000 );
PROVIDE ( APB_SARADC = 0x60040000 );
PROVIDE ( LCD_CAM = 0x60041000 );
PROVIDE ( USB0 = 0x60080000 );
PROVIDE ( USBH = 0x60080000 );
PROVIDE ( USB_WRAP = 0x60039000 );

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@ -66,7 +66,7 @@ if(NOT BOOTLOADER_BUILD)
"esp32s2/touch_sensor_hal.c"
"esp32s2/dac_hal.c"
"esp32s2/interrupt_descriptor_table.c"
"esp32s2/usbh_hal.c")
"usbh_hal.c")
endif()
if(${target} STREQUAL "esp32s3")
@ -81,7 +81,8 @@ if(NOT BOOTLOADER_BUILD)
"usb_hal.c"
"esp32s3/brownout_hal.c"
"esp32s3/interrupt_descriptor_table.c"
"esp32s3/touch_sensor_hal.c")
"esp32s3/touch_sensor_hal.c"
"usbh_hal.c")
endif()
if(${target} STREQUAL "esp32c3")

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@ -2,7 +2,7 @@ COMPONENT_SRCDIRS := . esp32
COMPONENT_ADD_INCLUDEDIRS := esp32/include include
COMPONENT_ADD_LDFRAGMENTS += linker.lf
COMPONENT_OBJEXCLUDE += ./spi_slave_hd_hal.o ./spi_flash_hal_gpspi.o ./spi_slave_hd_hal.o ./ds_hal.o ./gdma_hal.o ./lcd_hal.o ./systimer_hal.o ./usb_hal.o
COMPONENT_OBJEXCLUDE += ./spi_slave_hd_hal.o ./spi_flash_hal_gpspi.o ./spi_slave_hd_hal.o ./ds_hal.o ./gdma_hal.o ./lcd_hal.o ./systimer_hal.o ./usb_hal.o ./usbh_hal.o
ifndef CONFIG_ETH_USE_ESP32_EMAC
COMPONENT_OBJEXCLUDE += esp32/emac_hal.o

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@ -495,7 +495,7 @@ static inline bool usbh_hal_port_check_if_connected(usbh_hal_context_t *hal)
* @note This function should only be called after confirming that a device is connected to the host port
*
* @param hal Context of the HAL layer
* @return usb_priv_speed_t Speed of the connected device (FS or LS only on the esp32-s2)
* @return usb_priv_speed_t Speed of the connected device (FS or LS only on the esp32-s2 and esp32-s3)
*/
static inline usb_priv_speed_t usbh_hal_port_get_conn_speed(usbh_hal_context_t *hal)
{

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@ -443,13 +443,13 @@ static inline void usbh_ll_hcfg_set_fsls_pclk_sel(usbh_dev_t *hw)
static inline void usbh_ll_hcfg_set_defaults(usbh_dev_t *hw, usb_priv_speed_t speed)
{
hw->hcfg_reg.descdma = 1; //Enable scatt/gatt
hw->hcfg_reg.fslssupp = 1; //FS/LS supp only
hw->hcfg_reg.fslssupp = 1; //FS/LS support only
/*
Indicate to the OTG core what speed the PHY clock is at
Note: It seems like our PHY has an implicit 8 divider applied when in LS mode,
so the values of FSLSPclkSel and FrInt have to be adjusted accordingly.
*/
hw->hcfg_reg.fslspclksel = (speed == USB_PRIV_SPEED_FULL) ? 1 : 2; //esp32-s2 only supports FS or LS
hw->hcfg_reg.fslspclksel = (speed == USB_PRIV_SPEED_FULL) ? 1 : 2; //PHY clock on esp32-sx for FS/LS-only
hw->hcfg_reg.perschedena = 0; //Disable perio sched
}
@ -465,7 +465,7 @@ static inline void usbh_ll_hfir_set_defaults(usbh_dev_t *hw, usb_priv_speed_t sp
Note: It seems like our PHY has an implicit 8 divider applied when in LS mode,
so the values of FSLSPclkSel and FrInt have to be adjusted accordingly.
*/
hfir.frint = (speed == USB_PRIV_SPEED_FULL) ? 48000 : 6000; //esp32-s2 only supports FS or LS
hfir.frint = (speed == USB_PRIV_SPEED_FULL) ? 48000 : 6000; //esp32-sx targets only support FS or LS
hw->hfir_reg.val = hfir.val;
}
@ -550,7 +550,7 @@ static inline uint32_t usbh_ll_get_frame_list_base_addr(usbh_dev_t *hw)
static inline usb_priv_speed_t usbh_ll_hprt_get_speed(usbh_dev_t *hw)
{
usb_priv_speed_t speed;
//esp32-s2 only supports FS or LS
//esp32-s2 and esp32-s3 only support FS or LS
switch (hw->hprt_reg.prtspd) {
case 1:
speed = USB_PRIV_SPEED_FULL;

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@ -16,6 +16,7 @@
#include <stdint.h>
#include <assert.h>
#include <string.h>
#include "sdkconfig.h"
#include "hal/usbh_hal.h"
#include "hal/usbh_ll.h"
@ -70,7 +71,7 @@
* - Those bits proxy their interrupt through the USBH_LL_INTR_CHAN_CHHLTD bit
* - USBH_LL_INTR_CHAN_XCS_XACT_ERR is always unmasked
* - When USBH_LL_INTR_CHAN_BNAINTR occurs, USBH_LL_INTR_CHAN_CHHLTD will NOT.
* - USBH_LL_INTR_CHAN_AHBERR doesn't actually ever happen on our system )i.e., ESP32S2 and later):
* - USBH_LL_INTR_CHAN_AHBERR doesn't actually ever happen on our system (i.e., ESP32-S2, ESP32-S3):
* - If the QTD list's starting address is an invalid address (e.g., NULL), the core will attempt to fetch that
* address for a transfer descriptor and probably gets all zeroes. It will interpret the zero as a bad QTD and
* return a USBH_LL_INTR_CHAN_BNAINTR instead.
@ -94,7 +95,11 @@ static void set_defaults(usbh_hal_context_t *hal)
usbh_ll_internal_phy_conf(hal->wrap_dev); //Enable and configure internal PHY
//GAHBCFG register
usb_ll_en_dma_mode(hal->dev);
usb_ll_set_hbstlen(hal->dev, 1); //Use INCR AHB burst. MUST DO SO IN ESP32-S2 DUE TO ARBITER ERRATA.
#ifdef CONFIG_IDF_TARGET_ESP32S2
usb_ll_set_hbstlen(hal->dev, 1); //Use INCR AHB burst. See the ESP32-S2 and later chip ERRATA.
#elif CONFIG_IDF_TARGET_ESP32S3
usb_ll_set_hbstlen(hal->dev, 0); //Do not use USB burst INCR mode for the ESP32-S3, to avoid interference with other peripherals.
#endif
//GUSBCFG register
usb_ll_dis_hnp_cap(hal->dev); //Disable HNP
usb_ll_dis_srp_cap(hal->dev); //Disable SRP

File diff suppressed because it is too large Load Diff

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@ -1,7 +1,7 @@
idf_build_get_property(target IDF_TARGET)
#USB Host is currently only supported on ESP32-S2
if(NOT "${target}" STREQUAL "esp32s2")
#USB Host is currently only supported on ESP32-S2, ESP32S3 chips
if(NOT "${target}" MATCHES "^esp32s[2-3]")
return()
endif()

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@ -1,7 +1,7 @@
idf_build_get_property(target IDF_TARGET)
#USB Host is currently only supported on ESP32-S2
if(NOT "${target}" STREQUAL "esp32s2")
#USB Host is currently only supported on ESP32-S2, ESP32S3 chips
if(NOT "${target}" MATCHES "^esp32s[2-3]")
return()
endif()