alex/esp-idf
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139 Commits

Author SHA1 Message Date
Alexey Lapshin
c1445ff243 coredump: remove tests (moved to esp-coredump repo) 2023-05-16 13:04:27 +08:00
Roland Dobai
4c2afac355 Merge branch 'bugfix/fix_ignoring_provided_corefiles_in_espcoredump' into 'release/v4.4' 
tools: fix the missing chip type in esp-coredump when the board is not connected

See merge request espressif/esp-idf!22079
 2023-02-17 23:40:15 +08:00
Omar Chebib
2ef2271afd coredump: add support for stacks in external RAM 
Tasks having their stacks in SPIRAM can now be part of the coredump written to flash
 2023-02-15 17:46:54 +08:00
Aleksei Apaseev
d3eb5b2346 tools: fix the missing chip type in esp-coredump when the board is not connected 
Closes https://github.com/espressif/esp-idf/issues/10400
 2023-02-08 10:07:15 +08:00
Omar Chebib
7d0cd23531 coredump: custom core dump stack is now supported on Xtensa targets 2022-12-26 12:24:26 +01:00
Alexey Lapshin
a5a4543faf tools: add GDB version '11.2_20220823' as a tool 
GDB now is standalone tool separated from toolchain due to frequent updates.

Added installation tests for the new tool.

Coredump tests are changed because they were wrong, see explanation:
esp32 objdump:
    40084290 <esp_crosscore_int_send_yield>:
    ......
    /builds/espressif/esp-idf/components/esp_system/crosscore_int.c:145
    4008429c:    000090            retw

With previous GDB backtrace was:
    #0  0x4008429c in esp_crosscore_int_send_yield (core_id=0) at /builds/espressif/esp-idf/components/esp_system/crosscore_int.c:144

This commit fixes the backtrace with the right line number:
    #0  0x4008429c in esp_crosscore_int_send_yield (core_id=0) at /builds/espressif/esp-idf/components/esp_system/crosscore_int.c:145

Other tests changes have the same cause of fixing.

Closes https://github.com/espressif/esp-idf/issues/6334
 2022-10-10 18:43:27 +04:00
Omar Chebib
9a36ced294 espcoredump: add a test for coredump dumped sections 2022-02-22 02:38:00 +00:00
Omar Chebib
b868fd2a95 espcoredump: fix a bug where tracked DRAM data where not dumped 
Variables marked as COREDUMP_DRAM_ATTR will now be part of the core dump.

* Closes https://github.com/espressif/esp-idf/issues/8151
 2022-02-22 02:38:00 +00:00
Anton Maklakov
91696b9d6d coredump: update test data for toolchain 2021r2 2021-10-25 19:55:41 +07:00
Anton Maklakov
c402b82c1a coredump: Add some notes on how to generate test data 2021-10-13 15:06:41 +07:00
Shubham Patil
8ad9daea7d espcoredump: Parse bt for instruction fetch prohibited cause 2021-09-29 23:08:54 +05:30
Ivan Grokhotkov
e21e5aac64 esp_hw_support: update esp32s3 chip ID to the MP version 
- Update 7.2.5 chip ID (4) to 7.2.8 chip ID (9).
- Remove TODO in espcoredump regarding this mismatch.
 2021-09-13 15:16:45 +02:00
dmitry
5d859f1404 Add Esp32s3 to the coredump component. 
Add changed expected_output for esp32, esp32s2 and esp32c3. coredump tag update.
 2021-09-13 05:20:34 -04:00
Omar Chebib
92cf321677 freertos: add kconfig options for task snapshot functions 
Task snapshots is required by other modules that don't use gdbstub
or core dump. Add a Kconfig option to manage these possibilities.
 2021-09-01 15:13:48 +08:00
Omar Chebib
83c9e1b223 freertos: take tasks snapshot out of tasks.c source code 2021-08-16 10:29:36 +08:00
Marius Vikhammer
8b259d15f6 coredump: fix section name parsing in python utility 
elf.py assumed every section header name had its own string in
shstrtab, but multiple sections may reuse the same substring with
different offsets.
 2021-08-02 13:15:30 +08:00
Shubham Patil
2d2b066c01 espcoredump: Update expected output to fix test failures 2021-07-28 09:41:07 +05:30
Shubham Patil
3e84e5e668 Merge branch 'bugfix/xtensa_extra_info_register_values' into 'master' 
espcoredump.py: Parse EPS and EPC register values using register index

See merge request espressif/esp-idf!14448
 2021-07-27 10:22:41 +00:00
Fu Hanxi
12f0b55ca9 test(coredump): refactor coredump test and add esp32s2/esp32c3 tests 2021-07-22 10:17:59 +08:00
Shubham Patil
df12f22e37 espcoredump.py: Parse EPS and EPC register values using register index 2021-07-21 20:24:47 +05:30
Omar Chebib
f810d51327 coredump: simplify the implementation of esp_core_dump_image_erase function 
Closes https://github.com/espressif/esp-idf/pull/6949
 2021-06-21 11:26:09 +08:00
0xFEEDC0DE64
352dc6cf83 Fixed esp_core_dump_image_erase() for flash encryption with 16byte long write buffer 2021-06-21 10:50:47 +08:00
Sachin Parekh
46dc36233a coredump: Parse backtrace info for RISCV 
For RISCV, backtrace generation on device is not possible without
including and parsing DWARF sections. We extract the crash task stack
and let the host generate the backtrace
 2021-05-17 11:43:25 +05:30
Fu Hanxi
b972631658 feat(coredump): add esp32s2 and esp32c3 support 2021-04-26 20:44:23 +08:00
Fu Hanxi
d94423c1cf fix(coredump): pr_status pid padding should be uint16 2021-04-26 20:44:23 +08:00
Omar Chebib
837629814f coredump: core dump data check can now be parametrized 
Core dump integrity check can now be parametrized through menuconfig.
It can be performed on boot or ignored. When core dump is activated
in the menuconfig, the user can still check the core dump at any time
with the function `esp_core_dump_image_check()`.

Fix a bug where `esp_core_dump_image_get()` was not accessible
when core dump was disabled.

Closes https://github.com/espressif/esp-idf/issues/6620
 2021-04-19 13:05:32 +08:00
Shubham Patil
78e387c2bc espcoredump: Fix string truncation build failure 2021-04-14 14:42:09 +05:30
Michael (XIAO Xufeng)
8cfcf6da7a Merge branch 'bugfix/enable_gpio18_gpio19_esp32c3' into 'master' 
gpio: Disable USB JTAG when setting pins 18 and 19 as GPIOs on ESP32C3

Closes IDF-2964

See merge request espressif/esp-idf!12753
 2021-04-12 09:39:55 +00:00
Shubham Patil
356e2bbe6d espcoredump: On device core dump parsing to generate summary 2021-04-09 09:43:40 +05:30
Omar Chebib
cd79f3907d gpio: Disable USB JTAG when setting pins 18 and 19 as GPIOs on ESP32C3 
When `DIS_USB_JTAG` eFuse is NOT burned (`False`), it is not possible
to set pins 18 and 19 as GPIOs. This commit solves this by manually
disabling USB JTAG when using pins 18 or 19.
The functions shall use `gpio_hal_iomux_func_sel` instead of
`PIN_FUNC_SELELECT`.
 2021-04-08 14:01:18 +08:00
0xFEEDC0DE64
45de6f9c59 espcoredump erase review comments 2021-03-30 08:59:39 +00:00
0xFEEDC0DE64
a72f2e2257 coredump: Implemented esp_core_dump_image_erase() and esp_core_dump_image_get() now returns ESP_ERR_NOT_FOUND when partition is blank 
Closes https://github.com/espressif/esp-idf/pull/6631
 2021-03-30 08:59:39 +00:00
Omar Chebib
e533431095 espcoredump: Fix bugs related to (fake) stacks 
Add support to tasks stacks in RTC DRAM. Before this fix, any stack
in RTC DRAM would have been considered as corrupted, whichi is not
the case.
Fix a bug related to wrong parameters passed to esp_core_dump_get_stack.
Fix a bug reading fake stack memory, triggering a memory violation.

* Closes https://github.com/espressif/esp-idf/issues/6751
* Merges https://github.com/espressif/esp-idf/pull/6750
 2021-03-22 11:38:21 +08:00
Angus Gratton
fd164b82b6 Merge branch 'refactor/move_from_xtensa' into 'master' 
Movements from xtensa

Closes IDF-2164

See merge request espressif/esp-idf!10556
 2021-03-11 00:24:25 +00:00
Renz Bagaporo
10c5226095 ldgen: use uppercase keywords for flags 2021-03-01 14:19:34 +08:00
Renz Bagaporo
dbdc17cced ldgen: rename emit to surround 2021-03-01 14:19:34 +08:00
Renz Bagaporo
115b6ac0ac esp32: transfer coredump linker script blocks to ldgen 2021-03-01 14:19:34 +08:00
Renz Bagaporo
633ead5dcb esp32: move coredump sections and schemes to espcoredump 2021-03-01 14:19:34 +08:00
Renz Bagaporo
0f03f450ff esp_hw_support: create esp_cpu 
Create a esp_cpu header that contains CPU-related functions and
utilities.
 2021-02-26 13:34:29 +08:00
Anton Maklakov
3a629afb06 Merge branch 'feature/type_checking_python' into 'master' 
CI:Type checking of Python scripts

Closes IDF-2413

See merge request espressif/esp-idf!12287
 2021-02-26 03:06:37 +00:00
Angus Gratton
b4612a2f14 Merge branch 'feature/coredump_refactor_riscv_support' into 'master' 
espcoredump: code refactoring and add support for RISC-V implementation

Closes ESP-1758

See merge request espressif/esp-idf!11850
 2021-02-25 22:41:27 +00:00
Tomas Sebestik
a22597a2d6 Add mypy check to pre-commit-config 2021-02-25 07:05:43 +00:00
0xFEEDC0DE64
5a956f8b5e Fixed c++ include usage for esp_core_dump.h 2021-02-20 22:27:45 +01:00
Omar Chebib
e9996ebd4b espcoredump: code refactoring and add support for RISC-V implemetation 
This commit includes the refactoring of the core dump feature. Thanks to
this refactoring, it is easier to integrate the support of RISC-V
architecture for this feature.

Fixes ESP-1758
 2021-02-07 19:04:19 +08:00
Fu Hanxi
da73dc8195 fix(coredump): parse registers values from stack 2021-01-29 11:12:21 +08:00
Ivan Grokhotkov
88252c98b8 Merge branch 'feature/refactor_espcoredump' into 'master' 
Feature: Refactor espcoredump

See merge request espressif/esp-idf!11525
 2021-01-21 20:35:31 +08:00
Angus Gratton
3532f52f60 Merge branch 'bugfix/ldgen_ignore_nonexistent_archives_and_obj' into 'master' 
ldgen: check mappings

Closes IDF-1624

See merge request espressif/esp-idf!8557
 2021-01-21 15:59:35 +08:00
Fu Hanxi
be71f5050d core dump: modify the test according to the refactor 2021-01-21 15:14:59 +08:00
Fu Hanxi
d50f021a8c core dump: rewrite espcoredump.py with corefile package 2021-01-21 15:14:59 +08:00
Fu Hanxi
7109cda149 core dump: Add corefile package for parse/build bin/elf core files 
- elf.py: elf related structs

- gdb.py: gdb related functions

- loader.py: extract elf/bin from flash to elf format core file

- xtensa.py: xtensa arch target related structs and functions
 2021-01-21 15:14:59 +08:00