If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
registers (Flashboot protection included) will be re-enabled, and some
seconds later, will trigger an unintended reset.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
usb_serial_jtag: Improve the code for the issue of usb cdc device unable to work during sleep
Closes IDFGH-6887
See merge request espressif/esp-idf!20973
1. Remove RTC_CLOCK_BBPLL_POWER_ON_WITH_USB Kconfig option
During sleep, BBPLL clock always gets disabled
esp_restart does not disable BBPLL clock, so that first stage bootloader log can be printed
2. Add a new Kconfig option PM_NO_AUTO_LS_ON_USJ_CONNECTED
When this option is selected, IDF will constantly monitor USB CDC port connection status.
As long as it gets connected to a HOST, automatic light-sleep will not happen.
Closes https://github.com/espressif/esp-idf/issues/8507
Initialize the pmu sleep machine constant when pmu is initialized, and calculate
the pmu sleep time adjustment value and hardware configuration value according
to the machine constant during system sleep.
Calibrate fast OSC before each sleep and use the calibration value to calculate
PMU hardware wait cycles when use the fast OSC as the work clock.
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
Remove FPGA build for esp32c6
