harshal.patil
|
8445486303
|
fix(soc): Cleanup inaccessible SHA registers from the header files
|
2024-06-11 14:24:09 +05:30 |
|
Marius Vikhammer
|
a6c2c4149d
|
fix(intr): fixed intr threshhold min level on C5
|
2024-06-03 12:44:32 +08:00 |
|
Song Ruo Jing
|
665883229e
|
fix(gpio_etm): allow one GPIO binds to multiple ETM tasks
|
2024-04-24 15:58:49 +08:00 |
|
wuzhenghui
|
ffd5d1fd66
|
feat(esp_hw_support): support set clock divider for esp32p4 clock output
|
2024-04-17 15:09:54 +08:00 |
|
wuzhenghui
|
309725fcd0
|
feat(esp_hw_support): support esp32p4 clock output
|
2024-04-17 15:09:49 +08:00 |
|
wuzhenghui
|
101f1abbf1
|
refactor(esp_hw_support): add hal layer for clock output feature
|
2024-04-17 14:25:29 +08:00 |
|
Cao Sen Miao
|
0985bfbe27
|
feat(i2c_master): Add lp_i2c support in i2c master driver
|
2024-04-03 11:39:04 +08:00 |
|
xiehang
|
f3c5047638
|
feat(extconn): Supports external WiFi connections for ESP32p4 and other espressf chips
|
2024-04-01 11:44:52 +08:00 |
|
xiehang
|
9d7bd6a8dd
|
change(esp_phy): Add SOC_PHY_SUPPORTED to control phy mode
|
2024-04-01 11:36:55 +08:00 |
|
Li Shuai
|
59115cd2d1
|
change(esp_hw_support): some system peripherals to use a retention module number
|
2024-03-29 15:27:08 +08:00 |
|
Li Shuai
|
080d09387c
|
change(esp_hw_support): modify the style of module argument from bitmap to number
|
2024-03-29 15:22:52 +08:00 |
|
wuzhenghui
|
4a64d2fe2c
|
change(hal): control PAU bus clock by hal layer
|
2024-03-29 00:36:46 +08:00 |
|
wanlei
|
535afdd7f4
|
feat(esp32c61): ci enable header check, fix c61 build
|
2024-03-27 19:39:59 +08:00 |
|
Konstantin Kondrashov
|
8d6562d1f1
|
Merge branch 'feature/c5_c61_efuse_update' into 'master'
feat(efuse): Update efuses for C5 and C61
Closes IDF-8629 and IDF-8674
See merge request espressif/esp-idf!29627
|
2024-03-22 18:02:37 +08:00 |
|
Konstantin Kondrashov
|
25bc10e143
|
feat(efuse): Update efuses for C5 and C61
|
2024-03-21 18:37:46 +02:00 |
|
wanlei
|
a611e91b2f
|
feat(esp32c61): new chip add system and esp_timer support
|
2024-03-21 11:31:15 +08:00 |
|
wanlei
|
37dfd8fb52
|
feat(esp32c61): add G0 component support
|
2024-03-18 14:28:27 +08:00 |
|
wanlei
|
616c72b96c
|
feat(esp32c61): add & modify soc header files pass build (part 3/3)
|
2024-03-12 18:53:28 +08:00 |
|
wanlei
|
aec7aa3416
|
feat(esp32c61): add soc header files (2/2)
|
2024-03-06 11:42:14 +08:00 |
|
Wan Lei
|
84f27d65f6
|
Merge branch 'feat/c6lite_c61_introduce_step2_soc' into 'master'
feat(esp32c61): add soc peripheral header files (stage 2/8, part 1/2)
See merge request espressif/esp-idf!29353
|
2024-03-06 10:30:39 +08:00 |
|
wanlei
|
ee02b71f1c
|
feat(esp32c61): introduce target esp32c61
|
2024-03-01 21:12:25 +08:00 |
|
wanlei
|
5fef81609a
|
feat(esp32c61): add soc peripheral header files (1/2)
|
2024-03-01 18:09:13 +08:00 |
|