For some of the MSPI high frequency setting (e.g. 80M DDR mode Flash or PSRAM), timing tuning is required.
Certain delays will be added to the MSPI RX direction. When system clock switches down, the delays should be
cleared. When system clock switches up, the delays should be restored.
Replaced hyphens with underscores in examples
project definition for all examples which had
hyphens in their project name. dpp-enrollee is
an exceptions because the name matches the
project directory name while the project
directory also contains hyphens.
* On S3, the placement of ROM functions is
ECO-dependent. Hence, we don't jump into
the middle of the longjmp function in ROM
on S3 anymore.
Instead, the whole longjump function is used
in the patch.
* Also properly excluded the patch from
bootloader build with Makefiles
Closes IDF-3391
The previous location was the return from the first ets_printf call
that prints ROM sign-on message. Since the main function was patched
in ECO3, the new address no longer works — there is no instruction at
0x40007901 in ECO3 ROM. This could be solved by setting two
breakpoints (one would work for ECO <=2, the other for ECO3), but we
would need to remove the unused breakpoint later.
Fix this by setting the breakpoint at ets_printf. This means that when
debugging a loadable ELF the ROM sign-on message will no longer be
shown, but this doesn't seem to be an issue.
* Patched longjmp to be context-switch safe
longjmp modifies the windowbase and windowstart
registers, which isn't safe if a context switch
occurs during the modification. After a context
switch, windowstart and windowbase will be
different, leading to a wrongly set windowstart
bit due to longjmp writing it based on the
windowbase before the context switch. This
corrupts the registers at the next window
overflow reaching that wrongly set bit.
The solution is to disable interrupts during
this code. It is only 6 instructions long,
the impact shouldn't be significant.
The fix is implemented as a wrapper which
replaces the original first instructions of
longjmp which are buggy. Then, it jumps back
to execute the rest of the original longjmp
function.
Added a comparably reliable test to the
test apps.
By unchecking "Place panic handler code in IRAM" in the menuconfig,
the panic handlers will be placed in flash. Of course, flash cache must
be activated when entering panic handlers.
Theory is that on the runner, in rare cases, gdb may need more than
1 second to load and start responding to commands.
However it's possible these timeouts are due to some other problem
(like gdb failing)
The previous approach was to allocate an array on the stack, and
have the array extend past the stack size. This worked by would
result in SP being moved near the end of the stack. If an interrupt
triggered at that time, interrupt prologue would try to save the
context to the stack, tripping the stack overflow watchpoint.
Replacing this with the approach which doesn't move the SP and simply
writes to decreasing addresses from SP, until stack overflow check
triggers.
