ci: add flash psram test under different configs on esp32s3

.gitlab/ci/target-test.yml

@@ -303,6 +303,11 @@ example_test_ESP32C3_SDSPI:
     - .test_app_template
     - .rules:test:custom_test-esp32c3
 
+.test_app_esp32s3_template:
+  extends:
+    - .test_app_template
+    - .rules:test:custom_test-esp32s3
+
 test_app_test_001:
   extends: .test_app_esp32_template
   tags:
@@ -345,6 +350,24 @@ test_app_test_esp32_generic:
   variables:
     SETUP_TOOLS: "1"
 
+test_app_test_flash_psram_f4r4:
+  extends: .test_app_esp32s3_template
+  tags:
+    - ESP32S3
+    - MSPI_F4R4
+
+test_app_test_flash_psram_f4r8:
+  extends: .test_app_esp32s3_template
+  tags:
+    - ESP32S3
+    - MSPI_F4R8
+
+test_app_test_flash_psram_f8r8:
+  extends: .test_app_esp32s3_template
+  tags:
+    - ESP32S3
+    - MSPI_F8R8
+
 .component_ut_template:
   extends: .target_test_job_template
   variables:

tools/test_apps/system/flash_psram/CMakeLists.txt

@@ -0,0 +1,6 @@
+# The following lines of boilerplate have to be in your project's
+# CMakeLists in this exact order for cmake to work correctly
+cmake_minimum_required(VERSION 3.5)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(test_flash_psram)

tools/test_apps/system/flash_psram/README.md

@@ -0,0 +1,7 @@
+| Supported Targets | ESP32-S3 |
+| ----------------- | -------- |
+
+This project tests if Flash and PSRAM can work under different configurations.
+To add new configuration, create one more sdkconfig.ci.NAME file in this directory.
+
+If you need to test for anything other than flash and psram, create another test project.

tools/test_apps/system/flash_psram/app_test.py

@@ -0,0 +1,54 @@
+# SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: Apache-2.0
+
+
+import glob
+import os
+from typing import Any
+
+import ttfw_idf
+from tiny_test_fw import Utility
+
+
+def test_loop(env, config_names):  # type: (Any, Any) -> None
+
+    for name in config_names:
+        Utility.console_log("Checking config \"{}\"... ".format(name), end='')
+        dut = env.get_dut('flash_psram', 'tools/test_apps/system/flash_psram', app_config_name=name)
+        dut.start_app()
+        dut.expect('flash psram test success')
+        env.close_dut(dut.name)
+        Utility.console_log('done')
+
+
+# For F8R8 board (Octal Flash and Octal PSRAM)
+@ttfw_idf.idf_custom_test(env_tag='MSPI_F8R8', target=['esp32s3'])
+def test_flash8_psram8(env, _):  # type: (Any, Any) -> None
+
+    config_files = glob.glob(os.path.join(os.path.dirname(__file__), 'sdkconfig.ci.f8r8*'))
+    config_names = [os.path.basename(s).replace('sdkconfig.ci.', '') for s in config_files]
+    test_loop(env, config_names)
+
+
+# For F4R8 board (Quad Flash and Octal PSRAM)
+@ttfw_idf.idf_custom_test(env_tag='MSPI_F4R8', target=['esp32s3'])
+def test_flash4_psram8(env, _):  # type: (Any, Any) -> None
+
+    config_files = glob.glob(os.path.join(os.path.dirname(__file__), 'sdkconfig.ci.f4r8*'))
+    config_names = [os.path.basename(s).replace('sdkconfig.ci.', '') for s in config_files]
+    test_loop(env, config_names)
+
+
+# For F4R4 board (Quad Flash and Quad PSRAM)
+@ttfw_idf.idf_custom_test(env_tag='MSPI_F4R4', target=['esp32s3'])
+def test_flash4_psram4(env, _):  # type: (Any, Any) -> None
+
+    config_files = glob.glob(os.path.join(os.path.dirname(__file__), 'sdkconfig.ci.f4r4*'))
+    config_names = [os.path.basename(s).replace('sdkconfig.ci.', '') for s in config_files]
+    test_loop(env, config_names)
+
+
+if __name__ == '__main__':
+    test_flash8_psram8()
+    test_flash4_psram8()
+    test_flash4_psram4()

tools/test_apps/system/flash_psram/main/CMakeLists.txt

@@ -0,0 +1,2 @@
+idf_component_register(SRCS "test_flash_psram.c"
+                       INCLUDE_DIRS ".")

tools/test_apps/system/flash_psram/main/test_flash_psram.c

@@ -0,0 +1,160 @@
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include "sdkconfig.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "esp_system.h"
+#include "esp_check.h"
+#include "esp_attr.h"
+#if CONFIG_IDF_TARGET_ESP32S3
+#include "esp32s3/rom/spi_flash.h"
+#include "esp32s3/rom/opi_flash.h"
+#endif
+
+const static char *TAG = "SPI0";
+
+//-----------------------------------------SPI0 PSRAM TEST-----------------------------------------------//
+#if CONFIG_SPIRAM
+
+#if CONFIG_SPIRAM_MODE_OCT
+#define SPI0_PSRAM_TEST_LEN    (512 * 1024)
+#define LENGTH_PER_TIME        1024
+#else
+#define SPI0_PSRAM_TEST_LEN    (128 * 1024)
+#define LENGTH_PER_TIME        1024
+#endif
+
+static esp_err_t spi0_psram_test(void)
+{
+    printf("----------SPI0 PSRAM Test----------\n");
+
+    uint8_t *psram_wr_buf = (uint8_t *)heap_caps_malloc(LENGTH_PER_TIME, MALLOC_CAP_32BIT | MALLOC_CAP_SPIRAM);
+    if (!psram_wr_buf) {
+        printf("no memory\n");
+        abort();
+    }
+
+    uint32_t *psram_rd_buf = (uint32_t *)heap_caps_malloc(SPI0_PSRAM_TEST_LEN, MALLOC_CAP_32BIT | MALLOC_CAP_SPIRAM);
+    if (!psram_rd_buf) {
+        printf("no memory\n");
+        abort();
+    }
+
+    srand(399);
+    for (int i = 0; i < SPI0_PSRAM_TEST_LEN / LENGTH_PER_TIME; i++) {
+        for (int j = 0; j < sizeof(psram_wr_buf); j++) {
+            psram_wr_buf[j] = rand();
+        }
+        memcpy(psram_rd_buf + i * LENGTH_PER_TIME, psram_wr_buf, LENGTH_PER_TIME);
+
+        if (memcmp(psram_rd_buf + i * LENGTH_PER_TIME, psram_wr_buf, LENGTH_PER_TIME) != 0) {
+            printf("Fail\n");
+            free(psram_rd_buf);
+            free(psram_wr_buf);
+            return ESP_FAIL;
+        }
+    }
+
+    free(psram_rd_buf);
+    free(psram_wr_buf);
+    printf(DRAM_STR("----------SPI0 PSRAM Test Success----------\n\n"));
+    return ESP_OK;
+}
+#endif
+
+
+//-----------------------------------------SPI1 FLASH TEST-----------------------------------------------//
+#define SPI1_FLASH_TEST_LEN     512
+#define SECTOR_LEN              4096
+#define SPI1_FLASH_TEST_NUM     (SECTOR_LEN / SPI1_FLASH_TEST_LEN)
+#define SPI1_FLASH_TEST_ADDR    0x200000
+
+extern void spi_flash_disable_interrupts_caches_and_other_cpu(void);
+extern void spi_flash_enable_interrupts_caches_and_other_cpu(void);
+static DRAM_ATTR uint8_t rd_buf[SPI1_FLASH_TEST_LEN];
+static DRAM_ATTR uint8_t wr_buf[SPI1_FLASH_TEST_LEN];
+
+
+static IRAM_ATTR esp_err_t spi1_flash_test(void)
+{
+    printf(DRAM_STR("----------SPI1 Flash Test----------\n"));
+
+    //We need to use SPI1
+    spi_flash_disable_interrupts_caches_and_other_cpu();
+    uint32_t sector_num = SPI1_FLASH_TEST_ADDR / SECTOR_LEN;
+    esp_rom_spiflash_erase_sector(sector_num);
+    spi_flash_enable_interrupts_caches_and_other_cpu();
+
+    for (int i = 0; i < SPI1_FLASH_TEST_NUM; i++) {
+        for (int j = i + 10; j < SPI1_FLASH_TEST_LEN; j++) {
+            wr_buf[j] = j;
+        }
+
+        spi_flash_disable_interrupts_caches_and_other_cpu();
+        uint32_t test_flash_addr = SPI1_FLASH_TEST_ADDR + i * SPI1_FLASH_TEST_LEN;
+        esp_rom_spiflash_write(test_flash_addr, (uint32_t*)wr_buf, SPI1_FLASH_TEST_LEN);
+        esp_rom_spiflash_read(test_flash_addr, (uint32_t*)rd_buf, SPI1_FLASH_TEST_LEN);
+        spi_flash_enable_interrupts_caches_and_other_cpu();
+
+        if (memcmp(wr_buf, rd_buf, SPI1_FLASH_TEST_LEN) != 0) {
+            printf(DRAM_STR("error happened between 0x%x and 0x%x!!!!\n"), test_flash_addr, test_flash_addr + SPI1_FLASH_TEST_LEN);
+            for (int i = 0; i < SPI1_FLASH_TEST_LEN; i++) {
+                if (wr_buf[i] != rd_buf[i]) {
+                    printf(DRAM_STR("err: wr[%d]: 0x%02x -- rd[%d]: 0x%02x\n"), i, wr_buf[i], i, rd_buf[i]);
+                }
+            }
+            return ESP_FAIL;
+        }
+        memset(rd_buf, 0x0, SPI1_FLASH_TEST_LEN);
+    }
+
+    printf(DRAM_STR("----------SPI1 Flash Test Success----------\n\n"));
+
+    return ESP_OK;
+}
+
+//-----------------------------------------SPI0 FLASH TEST-----------------------------------------------//
+#define SPI0_FLASH_TEST_LEN    32
+#define SPI0_FLASH_TEST_BUF    {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, \
+                                0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}
+
+uint8_t flash_rd_buf[SPI0_FLASH_TEST_LEN] __attribute__((section (".flash.rodata"))) = SPI0_FLASH_TEST_BUF;
+extern int _flash_rodata_start;
+extern int _rodata_reserved_end;
+
+
+static IRAM_ATTR esp_err_t spi0_flash_test(void)
+{
+    printf("----------SPI0 Flash Test----------\n");
+    //Check if the flash_rd_buf is in .rodata
+    ESP_RETURN_ON_ERROR(((intptr_t)flash_rd_buf >= (intptr_t)_flash_rodata_start) && ((intptr_t)flash_rd_buf < (intptr_t)_rodata_reserved_end), TAG, "psram_rd_buf not in rodata");
+
+    uint8_t cmp_buf[SPI0_FLASH_TEST_LEN] = SPI0_FLASH_TEST_BUF;
+
+    for (int i = 0; i < SPI0_FLASH_TEST_LEN; i++) {
+        if (flash_rd_buf[i] != cmp_buf[i]) {
+            return ESP_FAIL;
+        }
+    }
+    printf(DRAM_STR("----------SPI0 Flash Test Success----------\n\n"));
+
+    return ESP_OK;
+}
+
+void app_main(void)
+{
+    ESP_ERROR_CHECK(spi0_flash_test());
+
+#if CONFIG_SPIRAM
+    ESP_ERROR_CHECK(spi0_psram_test());
+#endif
+    ESP_ERROR_CHECK(spi1_flash_test());
+
+    printf("flash psram test success\n");
+}

tools/test_apps/system/flash_psram/sdkconfig.ci.default

@@ -0,0 +1,2 @@
+CONFIG_IDF_TARGET="esp32s3"
+CONFIG_IDF_TARGET_ESP32S3=y

tools/test_apps/system/flash_psram/sdkconfig.ci.f4r4_120sdr

@@ -0,0 +1,5 @@
+# Legacy, F4R4, Flash 120M SDR, PSRAM disable
+
+CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
+CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y

tools/test_apps/system/flash_psram/sdkconfig.ci.f4r4_120sdr_120sdr

@@ -0,0 +1,7 @@
+# Legacy, F4R4, Flash 120M SDR, PSRAM 120M SDR
+
+CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
+CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_ESP32S3_SPIRAM_SUPPORT=y
+CONFIG_SPIRAM_SPEED_120M=y

tools/test_apps/system/flash_psram/sdkconfig.ci.f4r4_120sdr_40sdr

@@ -0,0 +1,7 @@
+# Legacy, F4R4, Flash 120M SDR, PSRAM 40M SDR
+
+CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
+CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_ESP32S3_SPIRAM_SUPPORT=y
+CONFIG_SPIRAM_SPEED_40M=y

tools/test_apps/system/flash_psram/sdkconfig.ci.f4r4_40sdr_120sdr

@@ -0,0 +1,7 @@
+# Legacy, F4R4, Flash 40M SDR, PSRAM 120M SDR
+
+CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
+CONFIG_ESPTOOLPY_FLASHFREQ_40M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_ESP32S3_SPIRAM_SUPPORT=y
+CONFIG_SPIRAM_SPEED_120M=y

tools/test_apps/system/flash_psram/sdkconfig.ci.f4r4_80sdr_80sdr

@@ -0,0 +1,7 @@
+# Legacy, F4R4, Flash 80M SDR, PSRAM 80M SDR
+
+CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
+CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_ESP32S3_SPIRAM_SUPPORT=y
+CONFIG_SPIRAM_SPEED_80M=y

tools/test_apps/system/flash_psram/sdkconfig.ci.f4r8_120sdr

@@ -0,0 +1,5 @@
+# Legacy, F4R8, Flash 120M SDR, PSRAM disable
+
+CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
+CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y

tools/test_apps/system/flash_psram/sdkconfig.ci.f4r8_80sdr_40ddr

@@ -0,0 +1,8 @@
+# Legacy, F4R8, Flash 80M SDR, PSRAM 40M DDR
+
+CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
+CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_ESP32S3_SPIRAM_SUPPORT=y
+CONFIG_SPIRAM_MODE_OCT=y
+CONFIG_SPIRAM_SPEED_40M=y

tools/test_apps/system/flash_psram/sdkconfig.ci.f4r8_80sdr_80ddr

@@ -0,0 +1,8 @@
+# Legacy, F4R8, Flash 80M SDR, PSRAM 80M DDR
+
+CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
+CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_ESP32S3_SPIRAM_SUPPORT=y
+CONFIG_SPIRAM_MODE_OCT=y
+CONFIG_SPIRAM_SPEED_80M=y

tools/test_apps/system/flash_psram/sdkconfig.ci.f8r8_120sdr

@@ -0,0 +1,8 @@
+# Legacy, F8R8, Flash 120M SDR, PSRAM disable
+
+CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
+CONFIG_ESPTOOLPY_OCT_FLASH=y
+CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR=y
+CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_ESP32S3_SPIRAM_SUPPORT=n

tools/test_apps/system/flash_psram/sdkconfig.ci.f8r8_40ddr_40ddr

@@ -0,0 +1,10 @@
+# Legacy, F8R8, Flash 40M DDR, PSRAM 40M DDR
+
+CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
+CONFIG_ESPTOOLPY_OCT_FLASH=y
+CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR=y
+CONFIG_ESPTOOLPY_FLASHFREQ_40M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_ESP32S3_SPIRAM_SUPPORT=y
+CONFIG_SPIRAM_MODE_OCT=y
+CONFIG_SPIRAM_SPEED_40M=y

tools/test_apps/system/flash_psram/sdkconfig.ci.f8r8_40ddr_80ddr

@@ -0,0 +1,10 @@
+# Legacy, F8R8, Flash 40M DDR, PSRAM 80M DDR
+
+CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
+CONFIG_ESPTOOLPY_OCT_FLASH=y
+CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR=y
+CONFIG_ESPTOOLPY_FLASHFREQ_40M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_ESP32S3_SPIRAM_SUPPORT=y
+CONFIG_SPIRAM_MODE_OCT=y
+CONFIG_SPIRAM_SPEED_80M=y

tools/test_apps/system/flash_psram/sdkconfig.ci.f8r8_80ddr_40ddr

@@ -0,0 +1,10 @@
+# Legacy, F8R8, Flash 80M DDR, PSRAM 40M DDR
+
+CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
+CONFIG_ESPTOOLPY_OCT_FLASH=y
+CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR=y
+CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_ESP32S3_SPIRAM_SUPPORT=y
+CONFIG_SPIRAM_MODE_OCT=y
+CONFIG_SPIRAM_SPEED_40M=y

tools/test_apps/system/flash_psram/sdkconfig.ci.f8r8_80ddr_80ddr

@@ -0,0 +1,10 @@
+# Legacy, F8R8, Flash 80M DDR, PSRAM 80M DDR
+
+CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
+CONFIG_ESPTOOLPY_OCT_FLASH=y
+CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR=y
+CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_ESP32S3_SPIRAM_SUPPORT=y
+CONFIG_SPIRAM_MODE_OCT=y
+CONFIG_SPIRAM_SPEED_80M=y

tools/test_apps/system/flash_psram/sdkconfig.ci.f8r8_80sdr_80ddr

@@ -0,0 +1,10 @@
+# Legacy, F8R8, Flash 80M SDR, PSRAM 80M DDR
+
+CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
+CONFIG_ESPTOOLPY_OCT_FLASH=y
+CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR=y
+CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_ESP32S3_SPIRAM_SUPPORT=y
+CONFIG_SPIRAM_MODE_OCT=y
+CONFIG_SPIRAM_SPEED_80M=y