Commit Graph

300 Commits

Author SHA1 Message Date
Michael (XIAO Xufeng)
69be7c4cc2 Merge branch 'feat/support_esp32c2_uart_v5.0' into 'release/v5.0'
uart: update console docs about frequency for ESP32-C2, move frequency of clock sources out of HAL (v5.0)

See merge request espressif/esp-idf!19690
2022-08-25 02:03:26 +08:00
morris
43876cb31b Merge branch 'bugfix/add_adc_oneshot_disable_ulp_enum_v5.0' into 'release/v5.0'
esp_adc: add adc ulp mode disable enum , and kconfig to enable dac output (v5.0)

See merge request espressif/esp-idf!19710
2022-08-23 16:07:30 +08:00
Armando
81007ee4ed esp_adc: add adc ulp mode disable enum
Prior to this commit, adc ulp is disabled by setting
adc_oneshot_unit_init_cfg_t::ulp_mode to false.

After this commit, a new enum `ADC_ULP_MODE_DISABLE` is added. So
setting `ulp_mode` to `ADC_ULP_MODE_DISABLE`, instead of `false`, to
disable the ulp mode.
2022-08-23 10:48:15 +08:00
Michael (XIAO Xufeng)
6ed15178b6 uart: move frequency of clock sources out of HAL 2022-08-22 14:28:12 +08:00
morris
c8b634ecfe rgb_lcd: deprecate esp_lcd_color_space_t 2022-08-18 10:59:16 +08:00
wuzhenghui
7cb9304b65 Clean IRAM and DRAM address space conversion macros 2022-07-29 17:07:39 +08:00
morris
d94432fea8 systimer: refactor hal to accomodate more xtal choices 2022-07-25 16:08:52 +08:00
morris
c4e84751a5 driver: fix public header exceptions for driver 2022-07-22 00:12:36 +00:00
morris
454d658309 rgb_lcd: workaround pclk polarity bug by setting mo>=2 2022-07-21 13:06:09 +00:00
laokaiyao
edee3ee3cd i2s: add slot sequence table
Closes: https://github.com/espressif/esp-idf/issues/9208

When I2S is configured into different modes, the slot sequence varies.
This commit updates slot sequence tables and corresponding descriptions
in (both code and programming guide).
2022-07-21 15:52:39 +08:00
laokaiyao
90866e99fb i2s: add basic examples for STD/TDM/PDM mode 2022-07-21 15:52:39 +08:00
morris
4154eaec93 sdm: clean up soc/hal/ll code 2022-07-20 14:59:50 +08:00
Song Ruo Jing
4734b1433b Merge branch 'bugfix/gpio_hal_coverity_fix' into 'master'
gpio: Fix ESP32S3 GPIO48 does not support hold function bug and Fix coverity report

Closes IDF-4901

See merge request espressif/esp-idf!18805
2022-07-19 21:37:15 +08:00
Armando (Dou Yiwen)
9f6f61345b Merge branch 'feature/adc_driver_ng' into 'master'
ADC Driver NG

Closes IDF-4560, IDF-3908, IDF-4225, IDF-2482, IDF-4111, IDF-3610, IDF-4058, IDF-3801, IDF-3636, IDF-2537, IDF-4310, IDF-5150, IDF-5151, and IDF-4979

See merge request espressif/esp-idf!17960
2022-07-19 21:28:31 +08:00
Cao Sen Miao
53580a62b5 I2C: Fullfill the I2C clock tree, and support 26M XTAL on ESP32-C2 2022-07-19 11:41:42 +08:00
Armando
5b523a3313 esp_adc: new esp_adc component and adc drivers 2022-07-15 18:31:00 +08:00
songruojing
0c4b9a0101 gpio: Fix HAL bad bit shift operation on gpio_num_t reported from coverity
All gpio hal and ll functions input arguments gpio_num_t are changed to uint32_t type.
Validation of gpio num should be guaranteed from the driver layer.
2022-07-15 16:51:25 +08:00
Jiang Jiang Jian
b610b47a83 Merge branch 'feature/esp32s3_memprot_additional_improvements' into 'master'
[System/Security] Memprot after-merge improvements (v5.0)

Closes IDF-5263 and IDF-5208

See merge request espressif/esp-idf!18893
2022-07-13 15:48:20 +08:00
Ivan Grokhotkov
5b54ae76d4 esp_timer, hal: add support for non-integer systimer frequency
When ESP32-C2 is paired with a 26 MHz XTAL, the systimer tick
frequency becomes equal to 26 / 2.5 = 10.4 MHz. Previously we always
assumed that systimer tick frequency is integer (and 1 MHz * power of
two, above that!).
This commit introduces a new LL macro, SYSTIMER_LL_TICKS_PER_US_DIV.
It should be set in such a way that:

1. SYSTIMER_LL_TICKS_PER_US / SYSTIMER_LL_TICKS_PER_US_DIV equals the
   actual systimer tick frequency,
2. and SYSTIMER_LL_TICKS_PER_US is integer.

For ESP32-C2 this means that SYSTIMER_LL_TICKS_PER_US = 52 and
SYSTIMER_LL_TICKS_PER_US_DIV = 5.

This introduced two possible issues:

1. Overflow when multiplying systimer counter by 5
   - Should not be an issue, since systimer counter is 52-bit, so
     counter * 5 is no more than 55-bit.
2. The code needs to perform:
   - divide by 5: when converting from microseconds to ticks
   - divide by 52: when converting from ticks to microseconds
   The latter potentially introduces a performance issue for the
   esp_timer_get_time function.
2022-07-11 12:24:37 +08:00
Martin Vychodil
0c87ae2a91 System/Security: Memprot API unified (ESP32S3)
Added missing features and improvements
2022-07-09 22:57:51 +02:00
Michael (XIAO Xufeng)
a58362a429 Merge branch 'feature/efuse_rev_major_minor' into 'master'
efuse: Adds major and minor versions

See merge request espressif/esp-idf!18255
2022-07-07 11:48:54 +08:00
Cao Sen Miao
e218723e0e I2C: Make I2C clock frequency accurate 2022-07-06 11:58:08 +08:00
KonstantinKondrashov
0f8ff5aa15 efuse: Adds major and minor versions and others 2022-07-05 14:38:27 +08:00
Martin Vychodil
339fcbf14d System/Security: Memprot API unified (ESP32S3)
Unified Memory protection API for all PMS-aware chips - ESP32S3 port
2022-06-20 02:36:44 +00:00
Omar Chebib
752026a174 Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master'
G0: RISC-V targets have now an independent G0 layer

See merge request espressif/esp-idf!17926
2022-06-16 11:53:39 +08:00
laokaiyao
28b8fc6a7e i2s: update documents for driver-NG 2022-06-15 10:30:04 +08:00
laokaiyao
0fe3bb8ab7 i2s: update examples and unit-tests 2022-06-15 10:29:06 +08:00
laokaiyao
621d0aa942 i2s: Introduced a brand new driver 2022-06-15 10:29:06 +08:00
Omar Chebib
5bcd9b2db8 G0: RISC-V targets have now an independent G0 layer
G0 doesn't depend on any G1+ layer for RISC-V based targets
2022-06-14 15:00:53 +08:00
Darian Leung
a8a3756b38 hal: Route CPU and Interrupt Controller HAL/LL to esp_cpu calls
This commit makes changes to cpu_ll.h, cpu_hal.h, and interrupt_controller_hal.h:

- Moved to esp_hw_support in order to be deprecated in the future
- HAL/LL API now route their calls to esp_cpu.h functions instead

Also updated soc_hal.h as follows:

- Removed __SOC_HAL_..._OTHER_CORES() macros as they dependend on cpu_hal.h
- Made soc_hal.h and soc_ll.h interfaces always inline, and removed soc_hal.c.

This commit also updates the XCHAL_ERRATUM_572 workaround by

- Removing it's HAL function and invoking the workaround it directly the bootloader
- Added missing workaround for the ESP32-S3
2022-06-14 14:40:03 +08:00
morris
843279d287 rgb_lcd: support fractional clock divisor 2022-06-14 02:20:47 +00:00
morris
5daa73d236 Merge branch 'refactor/mcpwm_hal_driver_doc' into 'master'
mcpwm: don't support disable carrier one-shot pulse

Closes IDFGH-7406

See merge request espressif/esp-idf!18295
2022-06-10 10:28:59 +08:00
Cao Sen Miao
6589daabb9 MMU: Add configurable mmu page size support on ESP32C2 2022-06-08 19:34:31 +08:00
morris
f7ff7ac4d0 mcpwm: clean up hal driver and add doc 2022-06-02 15:01:18 +08:00
Cao Sen Miao
6a2d3509dc spi_flash: Making XMC flash works more stable when brownout detected 2022-06-02 10:38:55 +08:00
Jiang Jiang Jian
f3922f1b7f Merge branch 'feature/flash_mmap_refactor' into 'master'
flash mmap: abstract R/W of MMU table instead of reg access

See merge request espressif/esp-idf!16882
2022-05-29 13:56:37 +08:00
Darian Leung
c45784b8c4 hal: Fix systimer counter value bit field
This commit fixes the systimer_counter_value_t by adding a resreved field so that the
type fills 64-bits.

Without the reserved field, when compiling with -O0 optimization, the unoccupied high
bits would not be initalized by the compiler, leading to systimer_hal_get_counter_value()
returning a garbage value.
2022-05-26 12:56:25 +00:00
songruojing
a5b09cf015 rtc_clk: Clean up some clock related enum and macro in soc/rtc.h, replace with new ones in
soc/clk_tree_defs.h
2022-05-24 22:59:41 +08:00
jiangguangming
9c6afee12f flash mmap: abstract R/W MMU table instead of reg access 2022-05-20 16:46:27 +08:00
morris
8138f8bb02 driver: remove deprecated code
that declared as deprecated in the previous release
2022-05-19 11:31:53 +08:00
Jing Li
ac0d16cdc8 Merge branch 'bugfix/fix_cannot_lslp_again_after_ulp_wakeup' into 'master'
sleep: fix cannot lightsleep again after a wakeup from ULP

Closes IDFGH-4396

See merge request espressif/esp-idf!17970
2022-05-13 22:25:23 +08:00
jingli
dd414b9305 esp_hw_‎support/sleep: ‎fix cannot lightsleep again after a wakeup from ULP
Since ulp wakeup signal are connected to ulp int raw(except esp32), we
need to clear ulp int raw before sleep when ulp wakeup enabled. Otherwise,
if the ulp int raw is already set, chip will not sleep properly.

Closes https://github.com/espressif/esp-idf/issues/6229
2022-05-12 17:57:08 +08:00
Marius Vikhammer
c8617fe965 docs: fix all doxygen warnings
Doxygen warnings would previously not result in a failed pipeline.
Fixed this as well as all current warnings.
2022-05-12 14:50:03 +08:00
morris
722fde218d uart: add default source clock for all targets 2022-05-09 11:26:30 +08:00
Armando (Dou Yiwen)
03aeac1dde Merge branch 'refactor/adc_hal_common_layer' into 'master'
adc: create common adc hal layer

See merge request espressif/esp-idf!17577
2022-05-08 15:45:56 +08:00
Armando
49747bb486 adc: create common adc hal layer 2022-05-07 19:20:44 +08:00
morris
2fb43820c2 driver_ng: implement new rmt driver
The legacy driver can't handle the breaking change between esp chips

very well.

And it's not elegant to extend new feature like DMA, ETM.

The new driver can return a opaque handle for each RMT channel.

An obvious transaction concept was also introduced.

TX and RX functionalities are splited out.
2022-05-07 10:34:50 +00:00
Cao Sen Miao
4418a855ba spi_flash: refactor the spi_flash clock configuration, and add support for esp32c2 2022-04-26 15:22:37 +08:00
laokaiyao
b99ced08a2 i2s: fix only right case
Closes: https://github.com/espressif/esp-idf/issues/8538
2022-04-23 07:38:45 +00:00
Darian Leung
09dc46552b twai: Fix twai_ll_parse_frame_buffer() typo
Closes https://github.com/espressif/esp-idf/issues/8743
2022-04-22 15:25:39 +08:00