Commit Graph

161 Commits

Author SHA1 Message Date
Armando
260ee86c37 rtc: united sar peripheral control 2022-10-27 16:51:25 +08:00
Song Ruo Jing
6d24e8bcf4 gpio: Add support for esp32c6 2022-10-18 12:38:36 +08:00
morris
b562754a2f rmt: support esp32c6 2022-09-17 04:56:49 +00:00
laokaiyao
bae4944b90 i2s: bringup i2s on esp32c6 2022-09-15 20:03:39 +08:00
laokaiyao
7197e987cb i2s: add XTAL clock source 2022-09-15 19:32:06 +08:00
morris
5f550b2a13 rmt,gptimer: don't support rc_fast clock source for c6 and h2
The RC_FAST clock source on ESP32C6 and ESP32H2 can't be calibrated.
Which makes it impossible to work stable for peripherals like timer, RMT
2022-09-14 14:40:28 +00:00
morris
a1030307f1 gptimer: bringup driver on esp32c6 2022-09-13 10:50:58 +08:00
gaoxu
5934ba731e SPI: Fix SPI wrong dummy bits on ESP32H2 2022-09-09 01:54:53 +00:00
Simon
e923c15859 Merge branch 'refactor/i2c_hal' into 'master'
I2C: Refactor i2c hal and ll(pre-MR of I2C driver-NG)

See merge request espressif/esp-idf!19750
2022-09-02 10:47:35 +08:00
Cao Sen Miao
31b88a4c88 I2C: Refactor i2c hal and ll 2022-09-01 15:53:59 +08:00
wuzhenghui
1d299a8976 esp32c6: add hal support 2022-09-01 12:37:51 +08:00
wuzhenghui
c31aaeda2a ll: add reset interface to rtc_cntl_ll 2022-08-31 01:59:36 +00:00
Gao Xu
0da21aca0d Merge branch 'bugfix/fix_spi_hd_quad_issue_esp32c3' into 'master'
essl_spi: fix wrong dummy cycle under quad spi mode ant add a test to verify spi quad mod

Closes IDF-5182 and IDF-5181

See merge request espressif/esp-idf!18680
2022-08-30 10:53:11 +08:00
morris
995b89fbb6 gptimer: add API to get captured count value 2022-08-25 17:55:19 +08:00
gaoxu
3610b14aef SPI : fix wrong dummy cycle on quad mode and put get-command function in spi_ll.h
1.The dummy_bits is set to 4 in ESP32C3/C2, therefore, the data transmission started too early.This commit fix this issue by changing dummy_bits to 8.
2.Put the spi command the spi defintion in spi_types.h
3.Put the function which get spi command or dummy bits in spi_ll.h
2022-08-23 10:46:56 +08:00
Song Ruo Jing
72a15e3c7a Merge branch 'bugfix/gpio_usb_pin_pupd' into 'master'
gpio: fix USB D+ pin cannot disable pullup

Closes IDFGH-7984

See merge request espressif/esp-idf!19191
2022-08-22 17:18:05 +08:00
songruojing
01143bd732 gpio: fix USB D+ pin cannot disable pullup
Internally, disable usb serial jtag DP pin's pullup when calling gpio_ll_pullup_dis and rtcio_ll_pullup_disable
At usb serial jtag setup/install, re-enable DP pin's pullup

Closes https://github.com/espressif/esp-idf/issues/9495
2022-08-19 15:05:28 +08:00
Michael (XIAO Xufeng)
746f4b814c uart: move frequency of clock sources out of HAL 2022-08-15 18:55:43 +00:00
morris
6f2ac1ce2a rmt: add iram safe test
Closes https://github.com/espressif/esp-idf/issues/9487
2022-08-12 11:30:14 +08:00
morris
cf4cfc69ed esp_adc: add test with -O0 2022-08-02 23:07:06 +08:00
morris
a5a171926b rmt: add test with -O0 2022-08-02 23:07:06 +08:00
morris
031adc01c4 gpio: add test with -O0 2022-08-02 23:07:06 +08:00
morris
7faf1bee73 gptimer: add test with -O0 2022-08-02 22:53:36 +08:00
Armando
f325ad2211 mmu: fix wrong mmu end check
In mmu code, we follow the rule that the `end` address shouldn't be
touched. This commit fix wrong end address check in mmu_ll.h
2022-07-27 10:22:09 +00:00
morris
d94432fea8 systimer: refactor hal to accomodate more xtal choices 2022-07-25 16:08:52 +08:00
laokaiyao
edee3ee3cd i2s: add slot sequence table
Closes: https://github.com/espressif/esp-idf/issues/9208

When I2S is configured into different modes, the slot sequence varies.
This commit updates slot sequence tables and corresponding descriptions
in (both code and programming guide).
2022-07-21 15:52:39 +08:00
laokaiyao
90866e99fb i2s: add basic examples for STD/TDM/PDM mode 2022-07-21 15:52:39 +08:00
morris
4154eaec93 sdm: clean up soc/hal/ll code 2022-07-20 14:59:50 +08:00
Song Ruo Jing
4734b1433b Merge branch 'bugfix/gpio_hal_coverity_fix' into 'master'
gpio: Fix ESP32S3 GPIO48 does not support hold function bug and Fix coverity report

Closes IDF-4901

See merge request espressif/esp-idf!18805
2022-07-19 21:37:15 +08:00
Armando (Dou Yiwen)
9f6f61345b Merge branch 'feature/adc_driver_ng' into 'master'
ADC Driver NG

Closes IDF-4560, IDF-3908, IDF-4225, IDF-2482, IDF-4111, IDF-3610, IDF-4058, IDF-3801, IDF-3636, IDF-2537, IDF-4310, IDF-5150, IDF-5151, and IDF-4979

See merge request espressif/esp-idf!17960
2022-07-19 21:28:31 +08:00
Cao Sen Miao
53580a62b5 I2C: Fullfill the I2C clock tree, and support 26M XTAL on ESP32-C2 2022-07-19 11:41:42 +08:00
Armando
5b523a3313 esp_adc: new esp_adc component and adc drivers 2022-07-15 18:31:00 +08:00
songruojing
0c4b9a0101 gpio: Fix HAL bad bit shift operation on gpio_num_t reported from coverity
All gpio hal and ll functions input arguments gpio_num_t are changed to uint32_t type.
Validation of gpio num should be guaranteed from the driver layer.
2022-07-15 16:51:25 +08:00
Ivan Grokhotkov
5b54ae76d4 esp_timer, hal: add support for non-integer systimer frequency
When ESP32-C2 is paired with a 26 MHz XTAL, the systimer tick
frequency becomes equal to 26 / 2.5 = 10.4 MHz. Previously we always
assumed that systimer tick frequency is integer (and 1 MHz * power of
two, above that!).
This commit introduces a new LL macro, SYSTIMER_LL_TICKS_PER_US_DIV.
It should be set in such a way that:

1. SYSTIMER_LL_TICKS_PER_US / SYSTIMER_LL_TICKS_PER_US_DIV equals the
   actual systimer tick frequency,
2. and SYSTIMER_LL_TICKS_PER_US is integer.

For ESP32-C2 this means that SYSTIMER_LL_TICKS_PER_US = 52 and
SYSTIMER_LL_TICKS_PER_US_DIV = 5.

This introduced two possible issues:

1. Overflow when multiplying systimer counter by 5
   - Should not be an issue, since systimer counter is 52-bit, so
     counter * 5 is no more than 55-bit.
2. The code needs to perform:
   - divide by 5: when converting from microseconds to ticks
   - divide by 52: when converting from ticks to microseconds
   The latter potentially introduces a performance issue for the
   esp_timer_get_time function.
2022-07-11 12:24:37 +08:00
Michael (XIAO Xufeng)
a58362a429 Merge branch 'feature/efuse_rev_major_minor' into 'master'
efuse: Adds major and minor versions

See merge request espressif/esp-idf!18255
2022-07-07 11:48:54 +08:00
morris
a92cce9861 Merge branch 'bugfix/calib_i2c_clk' into 'master'
I2C: Make I2C clock frequency accurate

Closes IDF-5363

See merge request espressif/esp-idf!18686
2022-07-06 20:52:31 +08:00
Cao Sen Miao
e218723e0e I2C: Make I2C clock frequency accurate 2022-07-06 11:58:08 +08:00
GengYuchao
d145c337e0 Enable rpa_moudle reset function 2022-07-05 20:50:31 +08:00
KonstantinKondrashov
0f8ff5aa15 efuse: Adds major and minor versions and others 2022-07-05 14:38:27 +08:00
morris
7863c1bc45 Merge branch 'bugfix/fix_rtc_freq_err_for_h2_beta1' into 'master'
Bugfix/fix rtc freq err for h2 beta1

See merge request espressif/esp-idf!18682
2022-07-04 16:46:17 +08:00
Omar Chebib
cd48baf979 Refactor: move regi2c_*.h header files from esp_hw_support to soc component
When creating G0 layer, some regi2c_*.h headers were moved out from
esp_hw_support (G1) to soc (G0). In order to be consistent with that change,
move all the remaining regi2c_*.h headers to soc too.
2022-06-30 09:40:44 +00:00
GengYuchao
10fd1daa10 Add ETM clk gate defines for h2 2022-06-30 17:02:00 +08:00
Armando
31b3f31ef4 ext_mem: make memory region check strict 2022-06-28 14:17:44 +08:00
Mahavir Jain
dd24639215 Merge branch 'esp32h2/enable_ecc_accelerator' into 'master'
esp32h2: Enable ECC accelerator

Closes IDF-3397

See merge request espressif/esp-idf!18647
2022-06-23 20:06:26 +08:00
Cao Sen Miao
2c0651a671 Add regi2c enable/disable reference count 2022-06-23 15:36:44 +08:00
Cao Sen Miao
3a820462ac temperature_sensor: Add temperature sensor support for ESP32-C2 2022-06-23 15:36:43 +08:00
Sachin Parekh
6cfc9c365f esp32h2: Enable ECC accelerator 2022-06-23 12:59:13 +05:30
Omar Chebib
8fae0f0753 G0: Support Xtensa targets for G0-only compilation
G0-only example now supports Xtensa targets. This means that G0 layer
does not depend on G1+ layers anymore
2022-06-20 11:34:20 +00:00
Omar Chebib
752026a174 Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master'
G0: RISC-V targets have now an independent G0 layer

See merge request espressif/esp-idf!17926
2022-06-16 11:53:39 +08:00
laokaiyao
28b8fc6a7e i2s: update documents for driver-NG 2022-06-15 10:30:04 +08:00