1. Add conditions based on Kconfig options for functions which are
compiled based on those options.
2. Static allocation is always enabled, move corresponding functions
into the common list.
Since dd849ffc, _rodata_start label has been moved to a different
linker output section from where the TLS templates (.tdata, .tbss)
are located. Since link-time addresses of thread-local variables are
calculated relative to the section start address, this resulted in
incorrect calculation of THREADPTR/$tp registers.
Fix by introducing new linker label, _flash_rodata_start, which points
to the .flash.rodata output section where TLS variables are located,
and use it when calculating THREADPTR/$tp.
Also remove the hardcoded rodata section alignment for Xtensa targets.
Alignment of rodata can be affected by the user application, which is
the issue dd849ffc was fixing. To accommodate any possible alignment,
save it in a linker label (_flash_rodata_align) and then use when
calculating THREADPTR. Note that this is not required on RISC-V, since
this target doesn't use TPOFF.
Noted as a problem with thread local storage returning a different task's
pointers, but some other were APIs also accessing current task unsafely.
Regression in FreeRTOS 10 update a3c90bf59a
Causes test added in parent commit to pass.
This race happens if the deleted task is running on the other CPU,
and is already spinning in a critical section waiting for xTaskQueueMutex
because it's about to be blocked for a resource.
The "deleted" task would end up blocked, possibly indefinitely, and
never actually deleted or its resources cleaned up by the idle tasks.
Details:
vTaskDelete() adds the target task to the xTasksWaitingTermination list,
expecting it to be yielded off CPU and then cleaned up later. However as soon as
vTaskDelete() releases xTaskQueueMutex, the target task runs and moves itself to the
xDelayedTaskList1. Because interrupts are already disabled on that CPU,
the "yield" to the other CPU sent by the vTaskDelete() comes afterward so
doesn't help.
Fixes issue with DPORT init task, this task uses minimum stack size and may not be
enough if stack smashing detection is set to Overall mode.
Also reworks the way we calculate minimum stack to allow for adding multiple
contributing factors.
Closes https://github.com/espressif/esp-idf/issues/6403
Unless the option for "assert and keep running" is enabled.
This means that silent asserts now work for FreeRTOS, and disabling asserts
now also disables them in FreeRTOS without needing a separate config change.
Related to https://github.com/espressif/esp-idf/issues/6306
NOP instructions have been added in order to prevent the code
from executing code it shouldn't execute. This is due to a delay
between the moment an interrupt is requested and the moment it
is fired. It only happens on RISC-V SoC.
Enable shared stack watchpoint for overflow detection
Enable unit tests:
* "test printf using shared buffer stack" for C3
* "Test vTaskDelayUntil" for S2
* "UART can do poll()" for C3
Removed leftover code-paths that were never taken. Upstream freertos uses
vTaskSuspendAll() and xTaskResumeAll(), and therefor check if the task already
yielded.
In the IDF port of freertos we use critcal sections instead, so xAlreadyYielded
will never be set.
Partially addresses https://github.com/espressif/esp-idf/issues/6440
rtos_int_exit would store RA at an offset of 4 byte from the SP,
where the offset should be 0.
This caused rtos_int_exit to overwrite variables in bss.
The riscv vectors.S in riscv component contains the trap vector, which is responsible to
defer interrupts and examine if a task context switch is needed, this change cleans up
this code by hiding all freertos details behind on two functions rtos_it_enter/exit and
their implementations are placed in freertos riscv port files.
Add `xQueueGenericReceive` as that has been removed in FreeRTOS10.
This in turn breaks pre-builts libraries with earlier IDF releases
relying on this API.
Closes https://github.com/espressif/esp-wolfssl/issues/6
freertos: replace the freertos regular malloc to the specific malloc from xtensa port for tcb and stack allocations
freertos: avoid the cpu1 to unwind pended ticks when xTaskResumeAll is called insed of an ISR
freertos: protected the xPortGetCoreID functions with missing critical sections
tests: re-eanble the ignored tests that was failling before race-condition fixes
freertos/port: update the port files and split into xtensa and riscv ports
freertos: separated cpu files from rest of the kernel sources
freertos/port_xtensa: separated private include files into a folder
freertos/tasks: added task create pinned to core function do not break current IDF API
freertos/tasks: mimiced task create pinned function into tasks.c to do not break the IDF API.
freertos: freertos component now compiling
freertos: freertos component now building
freertos: moved critical sections outside from FR kernel section to portable section
portmacro_xtensa: add void indentifier on functions that take no arguments
freertos: fix critical sections implementation to match with their function prototype
freertos: add cmake changes of freertos into make
freertos: remove portDONT_DISCARD attribute from switch context function, it was breaking the docs building.
freertos: fix conflicitng types of vApplicationSleep function
license: update the license of freertos
freertos: Doxygen comments refactored to render them correctly on docs
freertos: added new functions of freertos into the documentation
freertos: added message buffers and stream buffers to documentation
sysview: update freertos system view to the compatible with version 10
freertos: fixed event group documentation rendering
freertos: update static task structure to match the actual tcb size
freertos: removed backported test functions
freertos/smp: brought SMP code to FreeRTOS 10 port
freertos/portmacro: added missing crosscore interrupt for yielding tasks
freertos: replaced soft-critical sections with hard-critical sections used by SMP
freertos: placed muxes inside of kernel objects
freertos: replaced original FR critical sections with SMP enabled spinlocks critical sections
freertos: moved xtensa port files to a separated folder
freertos: added multiple instance of global variables required to SMP
freertos: added SMP modifications on specific tasks module functions
freertos: added TLS deletion function to task module
freertos/tls: initialize TLS deletion callback to avoid crashing when calling task delete
freertos: modified vTaskDelete to do not erase current task that runs on other core
freertos: reverted taskhandle and timerhandle as void* type
freertos: fixed de-referencing void pointer to get run time counter
freertos: fix system view trace enter macro arguments
freertos: Replaced soft critical sections with spinlocks on event_groups
freertos: fixed tick function to avoid calling tick hooks twice
freertos: Nofity give checking per CPU if schedule is suspended
freertos: added mpu release on TCB deletion
freertos: Added SMP changes when deleting a TCB on idle task
freertos/license: update freertos license in COPYRIGHT.rst
freertos: unicore configurations can use task create pinned to core, it will be always pinned to core 0
freertos/portmacro: added cpu_hal_get_core_id() function instead of inline assembly
freertos/xtensa: update xtensa specific files used in master branch
newlib/locks: revert the preemption checking in lock acquisition and release
ref_clock: fix initial state of ref_clock interrupt handler
freertos: added missing critical sections and yielding checkings
freertos: remove magic numbers in vTaskDelete
freertos: added missing critical section in prvIsQueueEmpty
esp_system: removed repeated interrupt allocator code and moved common code to esp_system
xtens: moved xtensa specific code from freertos to the xtensa component
hal/interrupt_controller: added interrupt controller hal and ll files
docs: update the doxyfile with new location of esp_itr_alloc.h file
xtensa: fixed dangerous relocation problem after moving xtensa interrupt files out of freertos
docs: removed Xtensa reference from intr_allocator api-reference
xtensa: pushed the interrupt function that manages non iram interrupts to the xtensa layer
esp_system/test: fixed platform dependent setting for intr_allocator tests
hal: rename the functions used to manage non iram interrupt mask.
correct generation.py script to be silent when file: function is not in the object list (just ignore placement)
correct linker.lf to place task functions into flash if CONFIG_FREERTOS_TASK_FUNCTIONS_INTO_FLASH is active otherwise into IRAM
update kconfig option to place functions into IRAM
update linker file after tests
fix spi_device_polling_end crash when xTaskGetTickCount() in flash
disable "yield from lower priority task, other CPU" test case when placing rtos functions into flash
upadate ut app config freertos_flash
combine spi_flash driver and freertos ut configs into one file
remove TEST_EXCLUDE_COMPONENTS
ci: fix ut job
remove functions that are called from ISR funcs
add port module functions to place into Flash
place snapshot funcs into Flash when ESP_PANIC_HANDLER_IRAM is not set
ci: add job with tags UT_T1_GPIO,ESP32_IDF
Commit 891eb3b0 was fixing an issue with PS and EPC1 not being
preserved after the window spill procedure. It did so by saving PS in
a2 and EPC1 in a4. However the a4 register may be a live register of
another window in the call stack, and if it is overwritten and then
spilled to the stack, then the corresponding register value will end
up being corrupted. In practice the problem would show up as an
IllegalInstruction exception, when trying to return from a function
when a0 value was 0x40020.
Fix by using a0 register instead of a4 as scratch. Also fix a comment
about xthal_save_extra_nw, as this function in fact doesn't clobber
a4 or a5 because XCHAL_NCP_NUM_ATMPS is defined as 1.
Closes https://github.com/espressif/esp-idf/issues/5758
* changing dependencies from unity->cmock
* added component.mk and Makefile.projbuild
* ignore test dir in gen_esp_err_to_name.py
* added some brief introduction of CMock in IDF
CONFIG_FREERTOS_ISR_STACKSIZE was set to 2100 when ELF core dump was
enabled, which resulted in a non-16-byte-aligned interrupt stack
offset. This triggered "is SP corrupted" check in the backtrace,
terminating the backtrace early.
Fix the default value, and make sure that the stack is always aligned,
regardless of the value of CONFIG_FREERTOS_ISR_STACKSIZE.
This MR uses an intermediary function `start_app` to call after system
initialization instead of `app_main`.
In RTOS builds, freertos provides `start_app` and calls `app_main`.
In non-RTOS builds, user provides `start_app` directly.
Changes the startup flow to the ff:
hardware -> core libraries init -> other libraries init -> os
init (optional) -> app_main
- hardware init resides in the port layer, and is the entry point
- core libraries init executes init functions of core components
- other libraries init executes init functions of other components (weak
references)
- after other lib is init, the app_main function is called, however,
an OS can wrap the real call to app_main to init its own stuff, and
*then* call the real app_main
FreeRTOS scheduler uses additional stack space, as in some functions
variables are placed onto the stack instead of registers.
This issue resulted in occasional stack overflows in dport task, when
compiling at -O0 optimization level.
- Increase the configMINIMAL_STACK_SIZE to 1kB.
- Enable the watchpoint at the end of stack in CI startup test for
this optimization level.
This fixes the issue where XTOS_SET_INTLEVEL would lower INTLEVEL from
4 to 3, when eTaskGetState is invoked during the core dump, triggered
from the interrupt watchdog.
`xQueueGenericCreateStatic` is placed into flash by the linker script to
reduce IRAM usage. This will also cause the `xRingbufferCreate` not
not callable when cache is disabled.
The SPI bus lock on SPI1 introduces two side effects:
1. The device lock for the main flash requires the
`CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION` to be selected, however this
option is disabled by default in earlier IDF versions. Some developers
may find their project cannot be built by their old sdkconfig files.
2. Usually we don't need the lock on the SPI1 bus, due to it's
restrictions. However the overhead still exists in this case, the IRAM
cost for static version of semaphore functions, and the time cost when
getting and releasing the lock.
This commit:
1. Add a CONFIG_SPI_FLASH_BYPASS_MAIN_LOCK option, which will forbid the
space cost, as well as the initialization of the main bus lock.
2. When the option is not selected, the bus lock is used, the
`CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION` will be selected explicitly.
3. Revert default value of `CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION`
to `n`.
introduced in 49a48644e4.
Closes https://github.com/espressif/esp-idf/issues/5046
Configurable option to use IRAM as byte accessible memory (in single core mode) using
load-store (non-word aligned and non-word size IRAM access specific) exception handlers.
This allows to use IRAM for use-cases where certain performance penalty
(upto 170 cpu cycles per load or store operation) is acceptable. Additional configuration
option has been provided to redirect mbedTLS specific in-out content length buffers to
IRAM (in single core mode), allows to save 20KB per TLS connection.
1. Clarify THREADPTR calculation in FreeRTOS code, explaining where
the constant 0x10 offset comes from.
2. On the ESP32-S2, .flash.rodata section had different default
alignment (8 bytes instead of 16), which resulted in different offset
of the TLS sections. Unfortunately I haven’t found a way to query
section alignment from C code, or to use a constant value to define
section alignment in the linker script. The linker scripts are
modified to force a fixed 16 byte alignment for .flash.rodata on the
ESP32 and ESP32-S2beta. Note that the base address of .flash.rodata
was already 16 byte aligned, so this has not changed the actual
memory layout of the application.
Full explanation of the calculation below.
Assume we have the TLS template section base address
(tls_section_vma), the address of a TLS variable in the template
(address), and the final relocation value (offset). The linker
calculates:
offset = address - tls_section_vma + align_up(TCB_SIZE, alignment).
At run time, the TLS section gets copied from _thread_local_start
(in .rodata) to task_thread_local_start. Let’s assume that an address
of a variable in the runtime TLS section is runtime_address.
Access to this address will happen by calculating THREADPTR + offset.
So, by a series of substitutions:
THREADPTR + offset = runtime_address THREADPTR = runtime_address - offset
THREADPTR = runtime_address - (address - tls_section_vma + align_up(TCB_SIZE, alignment)) THREADPTR = (runtime_address - address) + tls_section_vma - align_up(TCB_SIZE, alignment)
The difference between runtime_address and address is same as the
difference between task_thread_local_start and _thread_local_start.
And tls_section_vma is the address of .rodata section, i.e.
_rodata_start. So we arrive to
THREADPTR = task_thread_local_start - _thread_local_start + _rodata_start - align_up(TCB_SIZE, alignment).
The idea with TCB_SIZE being added to the THREADPTR when computing
the relocation was to let the OS save TCB pointer in the TREADPTR
register. The location of the run-time TLS section was assumed to be
immediately after the TCB, aligned to whatever the section alignment
was. However in our case the problem is that the run-time TLS section
is stored not next to the TCB, but at the top of the stack. Plus,
even if it was stored next to the TCB, the size of a FreeRTOS TCB is
not equal to 8 bytes (TCB_SIZE hardcoded in the linker). So we have
to calculate THREADPTR in a slightly obscure way, to compensate for
these differences.
Closes IDF-1239
