alex/esp-idf
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121 Commits

Author SHA1 Message Date
Michael (XIAO Xufeng)
33db6d608e spi_slave: add HAL support 2019-05-20 07:34:34 +00:00
michael
0b523c2300 spi_master: fix the dual/quad io issue 
introduced in f871cc5ffa

The issue is caused by

1. The hal didn't pass the io_mode to LL.
2. The setup_device function overwrite the trans-specific settings.
 2019-04-27 01:36:47 +08:00
Angus Gratton
f871cc5ffa Merge branch 'feat/spi_hal_support' into 'master' 
spi_master: refactor and add HAL support

See merge request idf/esp-idf!4159
 2019-04-15 07:57:11 +08:00
morris
f5b03c9ea3 misc adjustment of esp32 component 2019-04-03 19:57:46 +08:00
Michael (XIAO Xufeng)
af2fc96ee1 spi_master: refactor and add HAL support 2019-03-28 17:14:50 +08:00
morris
c159984264 separate rom from esp32 component to esp_rom 
1. separate rom include files and linkscript to esp_rom
2. modefiy "include rom/xxx.h" to "include esp32/rom/xxx.h"
3. Forward compatible
4. update mqtt
 2019-03-21 18:51:45 +08:00
michael
b812520b19 spi_master: add support for variable dummy length in a same device 
Resolves https://github.com/espressif/esp-idf/issues/2741
 2019-02-27 02:13:33 +08:00
Michael (XIAO Xufeng)
155006243e spi_master: fix the timing a little so that can assign delay half clock manually 2019-01-26 00:10:41 +08:00
michael
435adaa22a spi_master: add check for trans len 
The driver decide whether use MOSI/MISO phases according to the buffer
address together with the SPI_TRANS_USE_*DATA. However someone may assue
that these phases will be skipped when the ``length``/``rxlength`` is
set to 0. In fact it is a feature that ``rxlength`` is allowed to be
set to 0 when tx and rx have the same length, and the driver fill the
``rxlength`` to ``length``.

An error check is added when the rxlength is 0 but there is data to be
sent.
 2018-11-26 03:49:26 +00:00
Michael (XIAO Xufeng)
8cddfa35b8 spi: fix the crash when callbacks are not in the IRAM 
Introduced in 9c23b8e5 and 4f87a62f. To get higher speed, menuconfig
options are added to put ISR and other functions into the IRAM.  The
interrupt flag ESP_INTR_FLAG_IRAM is also mistakenly set when the ISR is
put into the IRAM. However callbacks, which are wrote by the user, are
called in the master and slave ISR. The user may not be aware of that
these callbacks are not disabled during flash operations. Any cache miss
during flash operation will cause panic.

Essentially IRAM functions and intrrupt flag ESP_INTR_FLAG_IRAM are
different, the latter means not disabling the ISR during flash
operations.  New bus_config flag intr_flags is offered to help set the
interrupt attribute, including priority level, SHARED, IRAM (not
disabled during flash operations).  It introduced a small BREAK to
IDFv3.1 (but the same as IDFv3.0) that the user has to manually set IRAM
flag now (therefore he's aware of the IRAM thing) to void the ISR being
disabled during flash operations.
 2018-11-20 13:07:13 +08:00
michael
a52ab8ca87 spi_master: modify the error msg a little when over freq limit 
The MISO signal will be delayed if the GPIO matrix is enabled.
However, delay also comes from the slave.

Previous code only considers the former case, and assume the frequency
limitations is only violated when GPIO matrix is used.

Now we are able to calculate the freq limit when extenal MISO delay is
given (feature introduced in 9c6c6ec34ab0641ace89aeb9b1a133eb6fae1a18).
The frequency limit is lower when the external MISO delay is large, and
the limit is likely to be violated even with IOMUX.

Resolves https://github.com/espressif/esp-idf/issues/2690.
 2018-11-13 11:49:31 +08:00
Michael (XIAO Xufeng)
9b5d0f3322 spi: shown owner of spi host explicitly 2018-10-29 20:22:44 +08:00
Michael (XIAO Xufeng)
90d229eb6d spi_master: speed up polling performance by putting into IRAM 2018-10-25 12:31:45 +08:00
michael
e5ed450d95 spi: move gpio direction config to common func for coinsistence 
(MINOR CHANGE)
 2018-10-04 14:57:31 +08:00
Michael (XIAO Xufeng)
2600f43822 spi_master: fix the command and address field when LSB_FIRST enabled 
Resolves https://github.com/espressif/esp-idf/issues/2444.
 2018-10-04 14:57:30 +08:00
Michael (Xiao Xufeng)
4af51833f3 spi_master: add new polling mode to decrease time cost each transaction 2018-09-20 19:46:46 +08:00
Jeroen Domburg
4eb28b9ace Merge branch 'feature/spi_burst_desc' into 'master' 
spi_master: change to DMA burst mode when access descriptors

See merge request idf/esp-idf!2824
 2018-08-21 16:54:38 +08:00
michael
404e99965d spi_master: change high part config to allow transactions of 64 bytes 2018-08-16 18:55:09 +08:00
Michael (XIAO Xufeng)
203ceed1e7 spi_master: change to DMA burst mode when access descriptors 2018-08-08 13:56:01 +00:00
Angus Gratton
e5d2406b1d Merge branch 'bugfix/spi_cs_setup_fulldup' into 'master' 
fix(spi_master): allow to use cs_ena_pretrans in full duplex mode without…

See merge request idf/esp-idf!2576
 2018-07-16 16:30:36 +08:00
Michael (XIAO Xufeng)
3d23fe9a61 feature(spi): provide macro to write multi-byte data straightly 
resolves https://github.com/espressif/esp-idf/issues/2062
 2018-07-02 15:34:47 +08:00
michael
8676830e61 fix(spi_master): allow to use cs_ena_pretrans in full duplex mode without command and address phases 2018-06-25 04:30:14 +00:00
Angus Gratton
73f6fb9fe7 Merge branch 'feature/spi_functions_in_iram' into 'master' 
feature(spi_master): allow to place functions into IRAM to get higher efficiency

See merge request idf/esp-idf!2538
 2018-06-19 07:25:12 +08:00
Michael (XIAO Xufeng)
9c23b8e596 feature(spi_master): allow to place functions into IRAM to get higher efficiency 2018-06-14 20:22:40 +08:00
Michael (XIAO Xufeng)
77077196fd fix(spi): reset gpios that used by spi when deinited 2018-06-14 11:29:15 +08:00
Michael (XIAO Xufeng)
ebfda40b7c refactor(spi): move pin information into soc folder 2018-06-14 11:29:15 +08:00
Michael (XIAO Xufeng)
939e5693a5 chore(spi): fix the terms of native to iomux 2018-06-06 06:08:39 +00:00
michael
5cf7d3768d feat(spi_master): fine tune the timing of SPI 2018-06-06 06:08:39 +00:00
Michael (Xiao Xufeng)
45f8bcf3f8 fix(spi): allow using MISO on GPIO34-39 
Breaking Changes: arguments of ``spicommon_bus_initialize_io`` are changed.

Closes https://github.com/espressif/esp-idf/issues/1736.
 2018-04-12 17:01:38 +08:00
Michael (Xiao Xufeng)
77629129c0 chore(spi): update the return value of spi init functions 2018-04-12 17:01:38 +08:00
Michael (Xiao Xufeng)
7563510758 feat(spi_master): allow output high speed data when dummy bits are not used. 2018-03-26 21:24:32 +08:00
Jonathan Kaufmann
a99d4d5a7f Modified spi_bus_add_device so that it takes a constant *dev_config parameter. 
Merges https://github.com/espressif/esp-idf/pull/1690
 2018-03-19 12:17:45 +08:00
michael
f4be6ac84d fix(spi_master): fix the logic in the ISR to prevent re-config registers when device is not changed. 2017-12-28 12:03:29 +08:00
michael
7a7b8fc182 refactor(spi_master): move the clock calculation from ISR to initialization. 2017-12-28 12:03:28 +08:00
michael
02573a8dc9 fix(spi_master): release temporary memory when queue new trans timeout. 2017-11-17 12:15:19 +08:00
michael
57e1d47ad7 fix(spi_master): fix the CS pin issue with GPIO 0. 
Closes #909
 2017-11-17 12:15:19 +08:00
michael
0330ec270a feat(spi_master): add new feature allow use variable command and address field length for the same device. 
Closes #654
 2017-10-30 19:33:41 +08:00
Ivan Grokhotkov
e4616588b7 spi master: lock APB frequency while in transaction 2017-10-18 14:19:21 +08:00
Gabriel Carstoiu
8128bb95ef fix(spi_slave): enable DMA clock when initialization. 
merging in the code updates to the SPI master code done in commit b834fcf78a.

TW#15670, Closes #1027
 2017-10-17 12:20:40 +08:00
michael
074f36afff fix(spi_master): fix the heap corruption bug that RX DMA writes over the temporary buffer boundary. 
TW#15434

Closes #994.
 2017-09-19 16:47:14 +08:00
michael
b834fcf78a fix(spi_master): this fix the SPI MOSI output missing bug. 2017-09-04 22:43:51 +08:00
Ivan Grokhotkov
3161854efb Merge branch 'bugfix/spi_hd_rx' into 'master' 
fix(spi_dma_rx): add check to avoid using SPI half-duplex mode DMA with both MOSI and MISO phases.

See merge request !1111
 2017-08-28 17:36:58 +08:00
Ivan Grokhotkov
b636f81619 Merge branch 'bugfix/spi_command' into 'master' 
fix(spi_master): fix the command field to make it more intuitive to use.

See merge request !1119
 2017-08-28 10:29:56 +08:00
michael
0cb14f1648 fix(spi_dma_rx): add check to avoid using SPI half-duplex mode DMA with both MOSI and MISO phases. 2017-08-26 02:15:30 +08:00
michael
4c9754726f fix(spi_master): fix the command field to make it more intuitive to use. 2017-08-21 20:37:57 +08:00
michael
a01db5569c fix(spi_dma): fix the receive error with RX DMA start with non-aligned address. 2017-08-18 10:14:49 +08:00
Ivan Grokhotkov
159a2d01d1 Merge branch 'bugfix/spi_dma' into 'master' 
bugfix(spi_master): fix several issues when using RX DMA

See merge request !1006
 2017-08-16 18:55:25 +08:00
michael
ed1d084aea fix(spi_master): make the address field more intuitive to use. 
The address field should be placed at the highest bits of address and slv_wr_status registers. Instead of breaking the address into two parts and fill in each register, move the address to the highest bits and write to the registers respectively.

Breaking change: if you fill-in the SPI address filed in a previous version in some way and it works correctly, you still have to rewrite the address, in a more intuitive way.
 2017-08-15 14:49:31 +08:00
michael
366e4397e9 fix(spi_dma_rx): fixed the invalid argument issue in full-duplex mode. 
force rxlength=length and mosi=1 and inlink.start=1 on in full-duplex mode.
set rxlength > length is forbidden in full-duplex mode.

TW#12609, TW#14240, https://www.esp32.com/viewtopic.php?f=13&t=2519
 2017-08-14 17:25:30 +08:00
michael
227b011f6a fix(spi_master): fix SPI master, now able to transfer more than 32 bytes in non-DMA-accessable area. 
apply for internal space to hold these data.
use DMA when it's enabled, no matter long or short.

TW#12226, github#551
 2017-08-14 17:19:57 +08:00
Angus Gratton
8d7074ed5c soc: Move esp_ptr_dma_capable() function to soc_memory_layout.h 2017-07-10 17:46:03 +08:00
Angus Gratton
71c70cb15c heap: Refactor heap regions/capabilities out of FreeRTOS 
Remove tagged heap API, rename caps_xxx to heap_caps_xxx

Also includes additional heap_caps_xxx inspection functions.
 2017-07-10 17:46:03 +08:00
Jeroen Domburg
8af3fe4e84 Warn against and check for non-DMA-capable pointers being passed to SPI when DMA is used 2017-05-05 12:28:03 +08:00
devsaurus
530c3ca05c components/driver/spi_master: free dma descriptors 
Signed-off-by: Jeroen Domburg <jeroen@espressif.com>
 2017-05-05 11:13:42 +08:00
Jeroen Domburg
bf0c32364a SPI: Also check SPI_TRANS_USE_[T|R]XDATA when decifding to turn on MOSI/MISO. Fixes https://github.com/espressif/esp-idf/issues/488 2017-04-27 11:49:04 +08:00
Jeroen Domburg
881a90b8ab SPI: SPI master clock calculation: n has a minimum of 2 to allow for both a low and a high cycle. Fixes https://github.com/espressif/esp-idf/issues/491 2017-04-27 11:49:04 +08:00
Jeroen Domburg
4c06dca15c SPI: Small fixes according to MR comments 2017-04-27 11:49:04 +08:00
Jeroen Domburg
e9c372bc2d SPI: Split common SPI stuff out of master driver; add slave driver; add workaround for DMA issue. 2017-04-27 11:49:04 +08:00
Angus Gratton
fd3ef4cdfe Merge branch 'bugfix/github_fixes' into 'master' 
Various fixes from Github

Some one-line fixes from Github PRs.

See merge request !689
 2017-04-21 12:27:32 +08:00
Michael Kellner
eeb0aaa09e spidriver: Display length errors correctly 
SPI transfer length is bits, not bytes, so the error should indicate bits. Also, there are separate lengths for rx and
tx (confusingly named rxlength and length... if rxlength is 0, length is used). The code checks the tx length for the
rx, so it never validates rxlength.

Originally contributed as part of #511 https://github.com/espressif/esp-idf/pull/511
 2017-04-21 11:03:07 +10:00
Michel Pollet
349a77cb55 components/driver: 'const' all config calls. 
Some were, some weren't. They all could/should be.

Signed-off-by: Michel Pollet <buserror@gmail.com>
 2017-04-13 18:33:33 +01:00
Jeroen Domburg
76295c7a13 Fix timing adjustment needed for higher speeds of SPI master bus. 2017-03-28 11:31:59 +08:00
Jeroen Domburg
e35ebbf813 Use THRESH_DMA_TRANS define everywhere, make code match "smaller or equal" description 2017-02-21 18:27:56 +08:00
Lourens Naudé
04f7d96623 Fix SPI read edges in spi_intr 
Signed-off-by: Jeroen Domburg <jeroen@espressif.com>
 2017-02-21 18:26:03 +08:00
Dermot Duffy
33500f2561 Add missing variable initialisation. 
Signed-off-by: Jeroen Domburg <jeroen@espressif.com>
 2017-01-25 21:41:45 +08:00
Jeroen Domburg
356e01545c Add test for spi clock, fix corner cases) 2017-01-11 16:13:33 +08:00
Jeroen Domburg
daa2b7cbc9 n, h and l actually are 6-bit; they go from 1 to 64. 2017-01-11 14:13:37 +08:00
Jeroen Domburg
a98d07d650 Fix clock divider calculation 2017-01-11 13:01:48 +08:00
Jeroen Domburg
ee59fa75f4 Rename SPI Master IO pins to more common terminology, add better explanation to queue_length initialization value 2017-01-11 11:25:56 +08:00
Jeroen Domburg
5eb8eb3855 SPI master: rename transaction flags from SPI_* to SPI_TRANS_*, like the documentation says. Also add some explanation about the SPI signals in the documentation 2017-01-10 14:41:12 +08:00
Jeroen Domburg
23455de4c2 Add SPI Master driver, example, test and docs 2017-01-06 14:20:32 +08:00