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SPI: SPI master clock calculation: n has a minimum of 2 to allow for both a low and a high cycle. Fixes https://github.com/espressif/esp-idf/issues/491

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This commit is contained in:
Jeroen Domburg 2017-04-24 16:13:22 +08:00
parent cecb846450
commit 881a90b8ab
1 changed files with 1 additions and 1 deletions
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2
components/driver/spi_master.c
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@ -300,7 +300,7 @@ static int spi_set_clock(spi_dev_t *hw, int fapb, int hz, int duty_cycle) {
int bestpre=-1;
int besterr=0;
int errval;
for (n=1; n<=64; n++) {
for (n=2; n<=64; n++) { //Start at 2: we need to be able to set h/l so we have at least one high and one low pulse.
//Effectively, this does pre=round((fapb/n)/hz).
pre=((fapb/n)+(hz/2))/hz;
if (pre<=0) pre=1;