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140 Commits

Author SHA1 Message Date
songruojing
a5b09cf015 rtc_clk: Clean up some clock related enum and macro in soc/rtc.h, replace with new ones in 
soc/clk_tree_defs.h
 2022-05-24 22:59:41 +08:00
Jing Li
ac0d16cdc8 Merge branch 'bugfix/fix_cannot_lslp_again_after_ulp_wakeup' into 'master' 
sleep: fix cannot lightsleep again after a wakeup from ULP

Closes IDFGH-4396

See merge request espressif/esp-idf!17970
 2022-05-13 22:25:23 +08:00
jingli
ddcc5bfe38 improve ulp riscv test case 
Add second sleep and wakeup test in test case `ULP-RISC-V is able to wakeup main CPU from light sleep`
 2022-05-12 19:08:57 +08:00
Marius Vikhammer
c8617fe965 docs: fix all doxygen warnings 
Doxygen warnings would previously not result in a failed pipeline.
Fixed this as well as all current warnings.
 2022-05-12 14:50:03 +08:00
Sudeep Mohanty
f709faea7c ulp: Keep RTC_CNTL_COCPU_SHUT_RESET_EN set for ULP RISC-V 
RTC_CNTL_COCPU_SHUT_RESET_EN register was being reset during ULP RISC-V
initialization which does not let the ULP RISC-V coprocessor to reset
after it goes to halt. For proper operation of the coprocessor, it must
be reset after each cycle and hence this commit keeps
RTC_CNTL_COCPU_SHUT_RESET_EN set.
 2022-04-28 13:41:07 +05:30
Marius Vikhammer
d2872095f9 soc: moved kconfig options out of the target component. 
Moved the following kconfig options out of the target component:
 * CONFIG_ESP*_DEFAULT_CPU_FREQ* -> esp_system
 * ESP*_REV_MIN -> esp_hw_support
 * ESP*_TIME_SYSCALL -> newlib
 * ESP*_RTC_* -> esp_hw_support

Where applicable these target specific konfig names were merged into
a single common config, e.g;
CONFIG_ESP*_DEFAULT_CPU_FREQ -> CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
 2022-04-21 12:09:43 +08:00
Marius Vikhammer
2efd009dfb ulp: temporarily disable ULP support for S3 
Due to a hardware issue ULP support on S3 is temporarily disabled until a fixed is released.
Running ULP + sleep together can potentially cause permanent damage to the chip.
 2022-03-25 14:19:12 +08:00
Marius Vikhammer
0cd07d907e CI: disable S3 sleep related example tests 2022-03-21 11:56:01 +08:00
Anton Maklakov
e27f1331e4 components: correct printf() placeholder for time_t 
Using C99 %jd, https://en.cppreference.com/w/c/chrono/time_t
 2022-03-14 14:05:47 +07:00
Sudeep Mohanty
bc82613847 Merge branch 'docs/ulp_documentation_updates' into 'master' 
docs: Updated ULP documentation

Closes IDF-3306

See merge request espressif/esp-idf!17225
 2022-03-03 19:16:27 +08:00
Marius Vikhammer
706a14884f Merge branch 'feature/riscv_ulp_gpio_intr' into 'master' 
ULP: Add example of using GPIO to wakeup the ULP-RISCV processor

Closes IDFGH-6589

See merge request espressif/esp-idf!17288
 2022-03-03 09:40:03 +08:00
Sudeep Mohanty
4067bc40fc docs: Updated ULP documentation 
This commit updates documentation for ULP.
 2022-03-01 09:02:41 +05:30
Marius Vikhammer
c974a000d7 ULP: Add example of using GPIO to wakeup the ULP-RISCV processor 2022-02-28 14:15:25 +08:00
Sudeep Mohanty
4d8a0cce29 ulp: Added support for ULP FSM on esp32s3 and fixed bugs for esp32s2 
This commit enables ULP FSM support for esp32s3 and updates ULP FSM code
flow for other chips.
It adds C Macro support for the ULP FSM instruction set on esp32s2 and
esp32s3.
The unit tests are also updated to test ULP FSM on ep32s2 and esp32s3.
 2022-02-22 12:25:57 +05:30
Marius Vikhammer
8a48b55197 ulp: change deprecated headers to use relative includes to avoid recursivly including the same header 2022-02-11 14:56:11 +08:00
morris
ef00bd59dc esp_rom: extract int matrix route and cpu ticks getter 2022-02-09 13:52:20 +08:00
Sudeep Mohanty
2fc9bd61bf ulp: refactor ulp component 
This commit refactors the ulp component.
Files are now divided based on type of ulp, viz., fsm or risc-v.
Files common to both are maintained in the ulp_common folder.

This commit also adds menuconfig options for ULP within the ulp
component instead of presenting target specific configuations for ulp.
 2022-01-27 11:54:42 +05:30
Marius Vikhammer
ff6f927b5f ULP: add functions for stopping/restarting the ulp-riscv 
Closes https://github.com/espressif/esp-idf/issues/8232
 2022-01-20 11:34:53 +08:00
Sudeep Mohanty
2ed15d8b1e ulp: Added ULP RISC-V support for esp32s3 
This commit adds support for ULP RISC-V for esp32s3.

Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
 2022-01-18 10:58:00 +05:30
morris
869bed1bb5 soc: don't expose unstable soc header files in public api 2022-01-06 23:10:22 +08:00
Cao Sen Miao
eddc196081 esp_clk: refactor target/clk.h to private/esp_clk.h 2021-11-26 14:56:30 +08:00
Roland Dobai
766aa57084 Build & config: Remove leftover files from the unsupported "make" build system 2021-11-11 15:32:36 +01:00
Cao Sen Miao
599227a1b6 ESP8684: Add esp8684 target to other repo for passing build 2021-11-06 17:33:45 +08:00
Ivan Grokhotkov
0277ba7e4e ulp: fix quoting issues for linker script and map file arguments 2021-10-06 10:42:07 +02:00
Renz Bagaporo
7c22cccb9c esp32: cleanup build script 2021-07-16 20:14:27 +08:00
Shu Chen
6fce2930d0 esp32h2: enable more components to support esp32h2 
Involved components:
 * app_trace
 * esp-tls
 * esp_adc_cal
 * esp_pm
 * esp_serial_slave_link
 * esp_timer
 * freertos
 * idf_test
 * log
 * mbedtls
 * newlib
 * perfmon
 * spi_flash
 * spiffs
 * ulp
 * unity
 * vfs
 2021-07-01 19:53:11 +08:00
Angus Gratton
a041faec77 Merge branch 'feature/ulp_riscv_delay' into 'master' 
riscv-ulp: Add DS18B20 1wire RISCV-ULP example

Closes IDF-1746 and IDF-3456

See merge request espressif/esp-idf!14115
 2021-06-27 23:45:38 +00:00
Marius Vikhammer
386739595f RISCV-ULP: Add DS18B20 1wire RISCV-ULP example 2021-06-25 11:26:39 +08:00
Roland Dobai
407053592e Drop support for unsupported Python versions 2021-06-21 21:48:49 +02:00
Marius Vikhammer
bdfda351bd build docs: enable building of S3 docs 
* Added suport for building esp32s3 docs
 * Fixed all related warnings
 * Activated building of S3 docs for build HTML fast CI job
 2021-06-09 09:30:36 +08:00
Angus Gratton
52b555e1e0 esp32s2 riscv ulp: Make re-linking depend on linker script file 2021-05-06 09:25:32 +10:00
Angus Gratton
3ee4370578 esp32s2 riscv ulp: Ensure reset vector is always at offset 0x0 
Previous linker script relied on nothing else using the .text section

As reported at https://esp32.com/viewtopic.php?f=2&t=20734&p=75997
 2021-05-06 09:25:32 +10:00
Ivan Grokhotkov
e77a91df7f Merge branch 'doc/ulp_st_bits' into 'master' 
ulp: update ST instruction description (Github PR)

Closes IDFGH-3224

See merge request espressif/esp-idf!13159
 2021-04-26 07:15:15 +00:00
Michael (XIAO Xufeng)
06ec13e422 Merge branch 'bugfix/fix_co-cpu_riscv_ulp_ld_for_esp32s2' into 'master' 
bugfix: add .rodata section for riscv ulp for esp32s2

See merge request espressif/esp-idf!13109
 2021-04-19 07:49:58 +00:00
boarchuz
7e7c044afa update ulp st doc 
Merges https://github.com/espressif/esp-idf/pull/5222
 2021-04-15 16:16:11 +02:00
fuzhibo
357b64fd2c bugfix: add .rodata section for riscv ulp for esp32s2 2021-04-12 14:29:13 +08:00
Angus Gratton
9c2f180049 ulp: Fix bug where ULP linker script not regenerated for new config 
ULP linker script relies on value of CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM,
when this value changes in config then it should be regenerated.
 2021-03-31 19:25:35 +11:00
Angus Gratton
f7a8593a3b Merge branch 'style/python_isort_double_quote_fixer' into 'master' 
style: format python files with isort and double-quote-string-fixer

See merge request espressif/esp-idf!12149
 2021-01-27 12:25:39 +08:00
Fu Hanxi
0146f258d7 style: format python files with isort and double-quote-string-fixer 2021-01-26 10:49:01 +08:00
Renz Bagaporo
19d8a403e6 ulp: set riscv-ulp as done signal source properly 
Closes https://github.com/espressif/esp-idf/issues/6069
 2021-01-22 15:22:01 +08:00
Marius Vikhammer
68608f804c esp32c3: Misc fixes needed to build & run 2020-12-31 15:20:05 +11:00
Ivan Grokhotkov
de798541dc tools: use riscv32-esp-elf toolchain for ESP32-S2 RISC-V ULP 
riscv32-esp-elf toolchain (used for ESP32-C3) can also be used for
ESP32-S2 RISC-V ULP coprocessor.

This removes the riscv-none-embed-gcc toolchain which was originally
used for the ULP, and updates the docs and CMake files to use
riscv32-esp-elf.

Some flags are cleaned up and workarounds removed from CMake toolchain
file.
 2020-12-29 19:19:18 +00:00
martin.gano
f4ea2dcb74 Tools: add Python 2 deprecation warning 2020-12-02 11:08:48 +01:00
Angus Gratton
66fb5a29bb Whitespace: Automated whitespace fixes (large commit) 
Apply the pre-commit hook whitespace fixes to all files in the repo.

(Line endings, blank lines at end of file, trailing whitespace)
 2020-11-11 07:36:35 +00:00
Angus Gratton
e82eac4354 cmake: Apply cmakelint fixes 2020-11-11 07:36:35 +00:00
Dmitry Yakovlev
0a8afd13a2 Udate instruction set documentation for Esp32 and Esp32s2. 
Sleep instruction removed from S2 instruction set.
LDx/STx instructions descritioin fix offset range to 13 bits (11 bits signed 32 bit words offset).
Remove I2C RD/WR operations from S2.
 2020-10-17 02:44:47 +08:00
morris
9fa06719fa global: enable build uinit test for esp32-s3 2020-09-22 15:15:03 +08:00
morris
61f89b97c6 bringup esp32-s3 on FPGA 2020-09-22 15:15:03 +08:00
Ivan Grokhotkov
0efad5951b Merge branch 'bugfix/ulp_doc_typo' into 'master' 
ulp: typo fix (Github PR)

Closes IDFGH-1899

See merge request espressif/esp-idf!10382
 2020-09-15 01:11:25 +08:00
Ivan Grokhotkov
b6467257b9 Merge branch 'feature/cmock_component' into 'master' 
cmock as component replacing unity

See merge request espressif/esp-idf!9859
 2020-09-10 16:06:20 +08:00