esp32s2 riscv ulp: Ensure reset vector is always at offset 0x0

Previous linker script relied on nothing else using the .text section

As reported at https://esp32.com/viewtopic.php?f=2&t=20734&p=75997

components/ulp/ld/esp32s2.ulp.riscv.ld

@@ -12,6 +12,7 @@ SECTIONS
     . = ORIGIN(ram);
     .text :
     {
+        *start.S.obj(.text.vectors) /* Default reset vector must link to offset 0x0 */
         *(.text)
         *(.text*)
     } >ram

components/ulp/ulp_riscv/start.S

@@ -1,4 +1,4 @@
-	.section .text
+	.section .text.vectors
 	.global irq_vector
 	.global reset_vector
 
@@ -11,6 +11,8 @@ reset_vector:
 irq_vector:
 	ret
 
+	.section .text
+
 __start:
 	/* setup the stack pointer */
 	la sp, __stack_top