alex/esp-idf
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22,297 Commits 20 Branches 148 Tags 384 MiB
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102 Commits

Author SHA1 Message Date
Omar Chebib
049d21bb12 C/Cxx: unify static assertions with the macro ESP_STATIC_ASSERT 
Closes https://github.com/espressif/esp-idf/issues/9938
 2022-12-05 18:16:08 +08:00
Marius Vikhammer
92d018f4f1 esp-rom: fixed error in miniz header documention for tdefl_init 
Closes https://github.com/espressif/esp-idf/issues/8435
 2022-09-01 18:14:24 +08:00
jingli
236bd27134 further fix spi flash/ram current leakage 
Currently, we pull up cs io for spi flash/ram to reduce current leakage during
light sleep. But some kind of spi flash/ram chip need all io pull up. Otherwise,
current leakage will still exist.
 2022-07-28 13:11:55 +08:00
KonstantinKondrashov
dcc706280d reset_reasons: EFUSE_RST is treated as POWERON_RST 
ESP32 does not have the EFUSE_RST, the rest chips has this reset reason.
 2022-06-22 16:39:02 +08:00
Wu Zheng Hui
2e4784611d efuse: update efuse name (backport v4.4) 2022-05-30 11:15:16 +08:00
songruojing
b80a070395 esp_system: replace the range comparsion for reset reason in perip clk init with specific reset reason check, also add a test case in LEDC to check for the perip clk not being disabled after cpu reset 
(cherry picked from commit f57456e9dd919e5eea1d3cd0caa64b5c97a4df73)
 2022-01-27 09:51:00 +00:00
Mahavir Jain
9d73448272 Fix copyright headers for few include files 2021-12-28 14:29:33 +05:30
lovyan03
530a06cf61 bugfix: Conflicting declaration error with include<esp_efuse.h>, and Unified secure_boot.h include guard to "pragma once". 2021-12-28 14:29:28 +05:30
Li Shuai
e8188e5d8f ci: replacing old header with new SPDX header style 2021-10-20 11:36:23 +08:00
Li Shuai
881e1b0fd5 deep sleep: add deep sleep support for esp32s3 2021-10-20 11:36:20 +08:00
Jiang Jiang Jian
3b48b7e663 Merge branch 'Fix/update_reset_reason' into 'master' 
update reset reason for c3/s3/h2

See merge request espressif/esp-idf!14747
 2021-09-18 07:03:50 +00:00
wanglei
c3abbe3866 cache: Update cache.h and autoload api 2021-09-02 02:27:40 +08:00
SalimTerryLi
23e23b697c
rom/tjpgd: unify library & add rom patch 
remove external tjpgd library inside example

enable tjpgd decoding on all chips
 2021-09-01 14:42:17 +08:00
Mahavir Jain
d9fdb9dc3f esp_rom: remove "newlib.h" header 
We found conflict in "sizeof(time_t)" due to inclusion of this
header over toolchain specific "newlib.h".

Moreover, there are no users for this header and implementation
for API is also not available in ROM. Hence removing it.
 2021-08-27 14:33:05 +05:30
Sachin Parekh
2d82560ed5 bootloader: Enable Secure boot V2 for ESP32-S3 2021-08-19 14:08:12 +05:30
wuzhenghui
f913a10a22 update reset reason for c3/s3/h2 2021-08-13 17:45:53 +08:00
Li Shuai
d73a09cd8b light sleep: add wifi mac sleep support for esp32s3 2021-08-04 21:58:33 +08:00
Jakob Hasse
4dd88329c1 [esp_rom]: Partially buildable for linux 
The following files have been ported:
* esp_rom_crc.h
* esp_rom_sys.h
* esp_rom_efuse.h (mostly no-ops)
* esp_rom_md5.h

Integrated Linux-based rom implementation into log
and NVS component.

Added brief host tests for ROM to ensure basic
consistency on Linux.

Added ROM printf host unit tests.

Temporarily added reset reason for Linux in ROM.
 2021-08-03 12:03:24 +08:00
Song Ruo Jing
5d82d7c6ee Merge branch 'typo_fix/fix-length-typo' into 'master' 
docs: Fix length typo

Closes IDFGH-5272

See merge request espressif/esp-idf!14371
 2021-08-02 09:35:15 +00:00
Ato Araki
aea865b360 Fix length typo 
Closes https://github.com/espressif/esp-idf/pull/7037
 2021-07-29 14:44:43 +08:00
Cao Sen Miao
c29b3e2e36 spi_flash: move the unlock patch to bootloader and add support for GD 2021-07-29 10:46:33 +08:00
morris
1560d6f1ba soc: add reset reasons in soc component 2021-07-13 10:45:38 +08:00
Shu Chen
37f4cb8b4b esp32h2: add rom code for esp32h2 2021-07-01 19:53:11 +08:00
Angus Gratton
57fa883127 esp32s3: Remove APB frequency RTC register 
Usage of this register changed between ESP32-S3 beta2 and the
final chip.
 2021-06-29 17:38:46 +10:00
Armando
bc248278f8 spiflash: add octal spi psram support on 727 2021-06-25 19:41:57 +08:00
Marius Vikhammer
f124536948 system: add support for reset reason hint on S3 2021-06-15 13:39:51 +08:00
Anton Maklakov
b46b50eaa6 newlib: Add ESP_ROM_HAS_RETARGETABLE_LOCKING capability for C3 and S3 chips 2021-06-07 12:53:45 +07:00
Angus Gratton
9235754d4c esp_rom: Allow passing any type of data pointer to md5, remove unchecked size on digest pointer 2021-05-18 01:32:59 +00:00
Angus Gratton
ede477ea65 paritition_table: Verify the partition table md5sum when loading the app 
Additionally, always enable the partition MD5 check if flash encryption is on in
Release mode. This ensures the partition table ciphertext has not been modified
(CVE-2021-27926).

The exception is pre-V3.1 ESP-IDF bootloaders and partition tables, which
don't have support for the MD5 entry.
 2021-05-18 01:32:59 +00:00
Michael (XIAO Xufeng)
a0d13a31ec uart: fix misleading files for UART2 
Includes: header files, ld files and clk.c

ESP32-C3 only have UART0 and UART1.
 2021-04-27 17:40:19 +08:00
Marius Vikhammer
2aead8ba57 Support ESP32S3 Beta 3 target 
Update ROM API. Port changes from bringup branch.
 2021-03-18 10:24:22 +08:00
Angus Gratton
6a29b45bd4 secure boot v2: Fix issue checking multiple signature blocks on OTA update 2021-03-15 12:30:20 +00:00
KonstantinKondrashov
95564b4687 secure_boot: Secure Boot V2 verify app signature on update (without Secure boot) 
- ESP32 ECO3, ESP32-S2/C3/S3
 2021-03-15 12:30:20 +00:00
morris
0f5d1c1c46 rtc: supported disable rom log temporarily 2021-02-22 20:56:43 +08:00
KonstantinKondrashov
43ebb8ea61 efuse: Updates description of uart_print_control efuse 2021-02-08 18:02:55 +08:00
Cao Sen Miao
c1b41ece32 flash_encryption: Quick fixed the issue that block when flash_encryption_write, Related https://github.com/espressif/esp-idf/issues/6322, Related https://github.com/espressif/esp-idf/issues/6254 2021-02-05 20:10:42 +08:00
KonstantinKondrashov
98f726fa4b bootloader/esp32c3: Adds secure boot (not yet supported) 2021-01-19 20:51:13 +08:00
Chen Jian Xing
5b44295cb9 esp_wifi: fix esp32c3 code issues 
1. enable wifi clk and rm dport header
2.syn phy_init_data.h from esp32
 2021-01-10 16:16:28 +08:00
Angus Gratton
a5aac93051 esp_rom: Small changes for esp32c3 support 
Updated from internal commit 6d894813
 2020-12-24 13:40:01 +11:00
Angus Gratton
8929a9cdb1 Merge branch 'feature/aes_hal' into 'master' 
AES: refactor and add HAL layer

See merge request espressif/esp-idf!10979
 2020-12-11 15:39:49 +08:00
morris
c39476d699 esp_rom: added esp_rom_install_uart_printf 2020-12-11 11:45:10 +08:00
Marius Vikhammer
457ce080ae AES: refactor and add HAL layer 
Refactor the AES driver and add HAL, LL and caps.

Add better support for running AES-GCM fully in hardware.
 2020-12-10 09:04:47 +00:00
Angus Gratton
b68094199f esp_rom: Add initial ESP32-C3 support 
From internal commit 7761d6e8
 2020-11-30 11:12:56 +11:00
Cao Sen Miao
11188d2143 esp_flash:fix bug about clearing WLE automatically after actions 2020-11-12 16:44:29 +08:00
Angus Gratton
66fb5a29bb Whitespace: Automated whitespace fixes (large commit) 
Apply the pre-commit hook whitespace fixes to all files in the repo.

(Line endings, blank lines at end of file, trailing whitespace)
 2020-11-11 07:36:35 +00:00
Ivan Grokhotkov
48f27cb5ab Merge branch 'feature/esp32_ulp_allow_8kb' into 'master' 
esp32: allow up to 8 kB of ULP program size

Closes IDFGH-1772

See merge request espressif/esp-idf!10727
 2020-10-20 04:08:57 +08:00
Michael (XIAO Xufeng)
647dea9395 soc: combine xxx_caps.h into one soc_caps.h 
During HAL layer refactoring and new chip bringup, we have several
caps.h for each part, to reduce the conflicts to minimum. But this is
The capabilities headers will be relataive stable once completely
written (maybe after the featues are supported by drivers).

Now ESP32 and ESP32-S2 drivers are relative stable, making it a good
time to combine all these caps.h into one soc_caps.h

This cleanup also move HAL config and pin config into separated files,
to make the responsibilities of these headers more clear. This is
helpful for the stabilities of soc_caps.h because we want to make it
public some day.
 2020-10-17 16:10:15 +08:00
Marius Vikhammer
949fb8e63a SHA: add HAL layer and refactor driver 
Add a LL and HAL layer for SHA.
 2020-10-09 08:24:08 +00:00
Ivan Grokhotkov
ef10c2576f esp32: allow up to 8 kB of ULP program size 
The remaining 4 kB had been reserved for storing RF calibration and
BT stack state since 4e092be6. However, these features never got
implemented. If we ever need to place RF related data into RTC slow
memory, we can do this by creating a variable with RTC_NOINIT_ATTR
instead.

Closes https://github.com/espressif/esp-idf/issues/3993
 2020-10-05 11:41:39 +02:00
morris
61f89b97c6 bringup esp32-s3 on FPGA 2020-09-22 15:15:03 +08:00