- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
Remove FPGA build for esp32h2
Before this fix, when we call esp_pm_configure after gpio_wakeup_enable,
the configuration of GPIO in sleep state in gpio_wakeup_enable will be
overwritten by esp_pm_configure.
esp32c2: support feature(rtc time) depend on rtc fast mem
Closes IDF-3901, IDF-4239, IDF-5053, IDF-5060, and IDF-5131
See merge request espressif/esp-idf!19067
cpu retention: add riscv core sleep critical and non-critical register layout structure definition
cpu retention: add assembly subroutine for cpu critical register backup and restore
cpu retention: add cpu core critical register context backup and restore support
cpu retention: add cpu core non-critical register context backup and restore support
cpu retention: add interrupt priority register context backup and restore support
cpu retention: add cache config register context backup and restore support
cpu retention: add plic interrupt register context backup and restore support
cpu retention: add clint interrupt register context backup and restore support
cpu retention: wait icache state idle before pmu enter sleep
Initialize the pmu sleep machine constant when pmu is initialized, and calculate
the pmu sleep time adjustment value and hardware configuration value according
to the machine constant during system sleep.
Calibrate fast OSC before each sleep and use the calibration value to calculate
PMU hardware wait cycles when use the fast OSC as the work clock.
1. add check in the gdma driver, to prevent multiple channels connecting
to the same peripheral
2. memory copy DMA ID will occupy the peripheral's DMA ID on some ESP
targets (e.g. esp32c3/s3). We should search for a free one when
install async memcpy driver.
Closes https://github.com/espressif/esp-idf/issues/10575
Since DRAM and IRAM are superposed on esp32c6 it is not necessary to convert a freshly allocated
DRAM addr to its IRAM equivalent when MALLOC_CAP_EXEC is passed to heap_caps_malloc(). Instead,
proceed with a default allocation since the address returned by multi_heap_malloc() already belongs
to the IRAM region.
Applies for esp32c6 and every boards with superposed DRAM and IRAM addresses.
