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https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
pmu active state ICG map initialize and modify i2c master force enable to enable
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@ -27,7 +27,7 @@ bootloader_usable_dram_end = 0x4087c610;
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bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
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bootloader_dram_seg_len = 0x5000;
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bootloader_iram_loader_seg_len = 0x7000;
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bootloader_iram_seg_len = 0x2000;
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bootloader_iram_seg_len = 0x2100;
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/* Start of the lower region is determined by region size and the end of the higher region */
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bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -237,8 +237,8 @@ static inline void bootloader_hardware_init(void)
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esp_rom_spiflash_fix_dummylen(1, 1);
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#endif
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// TODO: IDF-5990 need update, enable i2c mst clk by force on temporarily
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SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_FORCE_ON_REG, MODEM_LPCON_CLK_I2C_MST_FO);
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/* Enable analog i2c master clock */
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SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
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SET_PERI_REG_MASK(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M);
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}
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -19,14 +19,47 @@
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#include "esp_hw_log.h"
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#include "sdkconfig.h"
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#include "esp_rom_uart.h"
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#include "esp_private/esp_pmu.h"
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#include "hal/clk_tree_ll.h"
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#include "hal/pmu_ll.h"
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#include "hal/modem_syscon_ll.h"
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#include "hal/modem_lpcon_ll.h"
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static const char *TAG = "rtc_clk_init";
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/**
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* Initialize the ICG map of some modem clock domains in the PMU_ACTIVE state
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*
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* A pre-initialization interface is used to initialize the ICG map of the
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* MODEM_APB, I2C_MST and LP_APB clock domains in the PMU_ACTIVE state, and
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* disable the clock gating of these clock domains in the PMU_ACTIVE state,
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* because the system clock source (PLL) in the system boot up process needs
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* to use the i2c master peripheral.
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*
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* ICG map of all modem clock domains under different power states (PMU_ACTIVE,
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* PMU_MODEM and PMU_SLEEP) will be initialized in esp_perip_clk_init().
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*/
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static void rtc_clk_modem_clock_domain_active_state_icg_map_preinit(void)
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{
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/* Configure modem ICG code in PMU_ACTIVE state */
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pmu_ll_hp_set_icg_modem(&PMU, PMU_MODE_HP_ACTIVE, PMU_HP_ICG_MODEM_CODE_ACTIVE);
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/* Disable clock gating for MODEM_APB, I2C_MST and LP_APB clock domains in PMU_ACTIVE state */
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modem_syscon_ll_set_modem_apb_icg_bitmap(&MODEM_SYSCON, BIT(PMU_HP_ICG_MODEM_CODE_ACTIVE));
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modem_lpcon_ll_set_i2c_master_icg_bitmap(&MODEM_LPCON, BIT(PMU_HP_ICG_MODEM_CODE_ACTIVE));
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modem_lpcon_ll_set_lp_apb_icg_bitmap(&MODEM_LPCON, BIT(PMU_HP_ICG_MODEM_CODE_ACTIVE));
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/* Software trigger force update modem ICG code and ICG switch */
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pmu_ll_imm_update_dig_icg_modem_code(&PMU, true);
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pmu_ll_imm_update_dig_icg_switch(&PMU, true);
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}
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void rtc_clk_init(rtc_clk_config_t cfg)
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{
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rtc_cpu_freq_config_t old_config, new_config;
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rtc_clk_modem_clock_domain_active_state_icg_map_preinit();
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/* Set tuning parameters for RC_FAST, RC_SLOW, and RC32K clocks.
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* Note: this doesn't attempt to set the clocks to precise frequencies.
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* Instead, we calibrate these clocks against XTAL frequency later, when necessary.
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