Michael (XIAO Xufeng)
f4aacbef9b
Merge branch 'feature/support_access_internal_i2c_register' into 'master'
...
feature(rtc): add new APIs support access internal i2c register
See merge request espressif/esp-idf!10039
2020-09-29 08:08:51 +08:00
fuzhibo
247789bb2e
rtc: support access internal i2c register
2020-09-27 12:12:17 +08:00
Renz Bagaporo
6462f9bfe1
esp32, esp32s2: create esp_pm component
2020-09-25 05:24:10 +00:00
Marius Vikhammer
3c14900a95
RSA: add max RSA bit len as a soc caps
2020-09-24 16:52:50 +08:00
Armando
1e1beb69aa
spi: fix build fail issue when target is esp32s3
2020-09-24 10:51:23 +08:00
Michael (XIAO Xufeng)
3c2f2aaffe
Merge branch 'docs/spi_flash_readme_update' into 'master'
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hal: Update readme aftering extracting hal document from soc document
See merge request espressif/esp-idf!10453
2020-09-23 13:33:08 +08:00
Cao Sen Miao
5baf124219
docs: update readme aftering extracting hal document from soc document
2020-09-23 11:47:23 +08:00
Renz Bagaporo
6d7606aee5
soc: remove unecessary compile line include dir orderding control
2020-09-23 02:53:03 +00:00
Renz Bagaporo
7f5893d53c
soc: move dac_hal to hal
2020-09-23 02:53:03 +00:00
Renz Bagaporo
01d9aa8070
soc: move mpu_hal test to hal component
2020-09-23 02:53:03 +00:00
Renz Bagaporo
2bcf99527c
soc: move out rtc_hal to hal component
2020-09-23 02:53:03 +00:00
morris
9fa06719fa
global: enable build uinit test for esp32-s3
2020-09-22 15:15:03 +08:00
morris
75a372a9f0
unit_test: support reference clock, test delay function
2020-09-22 15:15:03 +08:00
morris
61f89b97c6
bringup esp32-s3 on FPGA
2020-09-22 15:15:03 +08:00
Cao Sen Miao
d7e50c6457
spi_flash:bringup some flash supports for esp32s3
2020-09-22 15:15:03 +08:00
chenjianqiang
f19cabb7e4
psram: support psram for esp32s3
2020-09-22 15:15:03 +08:00
Angus Gratton
3f034a5005
spiram: Add soc macro for SPIRAM address space size, use it where applicable
...
Reference https://github.com/espressif/esp-idf/pull/5373
2020-09-21 11:43:55 +10:00
negativekelvin
5eb5bb5f72
Fix reserved psram region
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Closes https://github.com/espressif/esp-idf/pull/5373
Closes https://github.com/espressif/esp-idf/issues/5821
2020-09-21 11:39:54 +10:00
Michael (XIAO Xufeng)
fefdee1349
bootloader: fix the WRSR format for ISSI flash chips
...
1. The 2nd bootloader always call `rom_spiflash_unlock()`, but never help to clear the WEL bit when exit. This may cause system unstability.
This commit helps to clear WEL when flash configuration is done.
**RISK:** When the app starts, it didn't have to clear the WEL before it actually write/erase. But now the very first write/erase operation should be done after a WEL clear. Though the risk is little (all the following write/erase also need to clear the WEL), we still have to test this carefully, especially for those functions used by the OTA.
2. The `rom_spiflash_unlock()` function in the patch of ESP32 may (1) trigger the QPI, (2) clear the QE or (3) fail to unlock the ISSI chips.
Status register bitmap of ISSI chip and GD chip:
| SR | ISSI | GD25LQ32C |
| -- | ---- | --------- |
| 0 | WIP | WIP |
| 1 | WEL | WEL |
| 2 | BP0 | BP0 |
| 3 | BP1 | BP1 |
| 4 | BP2 | BP2 |
| 5 | BP3 | BP3 |
| 6 | QE | BP4 |
| 7 | SRWD | SRP0 |
| 8 | | SRP1 |
| 9 | | QE |
| 10 | | SUS2 |
| 11 | | LB1 |
| 12 | | LB2 |
| 13 | | LB3 |
| 14 | | CMP |
| 15 | | SUS1 |
QE bit of other chips are at the bit 9 of the status register (i.e. bit 1 of SR2), which should be read by RDSR2 command.
However, the RDSR2 (35H, Read Status 2) command for chip of other vendors happens to be the QIOEN (Enter QPI mode) command of ISSI chips. When the `rom_spiflash_unlock()` function trys to read SR2, it may trigger the QPI of ISSI chips.
Moreover, when `rom_spiflash_unlock()` try to clear the BP4 bit in the status register, QE (bit 6) of ISSI chip may be cleared by accident. Or if the ISSI chip doesn't accept WRSR command with argument of two bytes (since it only have status register of one byte), it may fail to clear the other protect bits (BP0~BP3) as expected.
This commit makes the `rom_spiflash_unlock()` check whether the vendor is issi. if so, `rom_spiflash_unlock()` only send RDSR to read the status register, send WRSR with only 1 byte argument, and also avoid clearing the QE bit (bit 6).
3. `rom_spiflash_unlock()` always send WRSR command to clear protection bits even when there is no protection bit active. And the execution of clearing status registers, which takes about 700us, will also happen even when there's no bits cleared.
This commit skips the clearing of status register if there is no protection bits active.
Also move the execute_flash_command to be a bootloader API; move
implementation of spi_flash_wrap_set to the bootloader
2020-09-19 10:51:51 +08:00
Angus Gratton
0fe231d2b3
Merge branch 'feature/pkg_ver_uses_4_bits' into 'master'
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efuse/esp32: Expands PKG_VER from 3 bit to 4 bits
Closes IDF-1919
See merge request espressif/esp-idf!9949
2020-09-17 18:21:08 +08:00
KonstantinKondrashov
2373f115fc
efuse/esp32: Expands PKG_VER from 3 bit to 4 bits
...
Closes: IDF-1919
2020-09-17 07:44:37 +00:00
morris
a3cc43485f
async memcpy: support async memcopy on esp32s2/s3
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Added async memory copy API:
on esp32-s2, the implementation is based on CP_DMA
on esp32-s3, the implementation is based on GDMA
2020-09-16 21:30:54 +08:00
Michael (XIAO Xufeng)
1a1e1911f9
Merge branch 'bugfix/spi_dma_close_before_cpu_reset' into 'master'
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spi: fix issue with closing DMA before CPU reset
Closes FCS-484
See merge request espressif/esp-idf!9844
2020-09-14 23:02:05 +08:00
Marius Vikhammer
b2f390df01
hal: update link to HAL readme.md
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The HAL readme was moved during refactoring, but links were not updated.
2020-09-11 15:48:08 +08:00
Jakob Hasse
20c068ef3b
cmock: added cmock as component
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* changing dependencies from unity->cmock
* added component.mk and Makefile.projbuild
* ignore test dir in gen_esp_err_to_name.py
* added some brief introduction of CMock in IDF
2020-09-02 16:38:37 +08:00
Michael (XIAO Xufeng)
5425ef4ee4
hal: extract hal component from soc component
2020-09-01 13:25:32 +08:00
Krzysztof Budzynski
94cc8fc4b3
Merge branch 'doc/tinyusb' into 'master'
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TinyUSB documentation
See merge request espressif/esp-idf!8862
2020-08-31 20:57:29 +08:00
Michael (XIAO Xufeng)
2b323e7180
Merge branch 'bugfix/fix_dac_driver_ut' into 'master'
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Driver(dac): fix DAC-DMA driver and unit test
Closes IDF-1407
See merge request espressif/esp-idf!8814
2020-08-31 00:05:34 +08:00
Andrei Gramakov
c863b4c777
docs: tinyusb documentation
2020-08-27 13:49:33 +02:00
fuzhibo
0914dfbb6a
dfiver(dac): add dac dma driver and unit test
2020-08-26 06:23:24 +00:00
fuzhibo
bd92e95160
driver(adc): add adc-dma code for esp32
2020-08-26 03:54:02 +00:00
me-no-dev
0aa1c13027
Fix USB CLK always reset and USB with swapped pins not working
2020-08-25 10:59:59 +03:00
Michael (XIAO Xufeng)
8a9dc46b14
Merge branch 'bugfix/spi_master_add_dummy_check' into 'master'
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spi_master: add dummy check when both mosi and miso are set
Closes IDF-1872 and IDF-266
See merge request espressif/esp-idf!9406
2020-08-23 12:47:18 +08:00
David Čermák
e2f72f449c
Merge branch 'feature/ethernet_flow_control' into 'master'
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ethernet: support flow control
Closes IDF-1207, WIFI-2510, WIFI-2290, WIFI-2291, WIFI-2507, WIFI-2508, WIFI-2612, and IDFGH-3465
See merge request espressif/esp-idf!9643
2020-08-21 14:33:30 +08:00
Armando
aa93347972
spi: remove spi4 related macros and codes
2020-08-17 21:32:15 +08:00
Renz Bagaporo
4f5135030f
esp_system: remove register level operations for timer wakeup
2020-08-17 19:09:24 +08:00
Renz Bagaporo
0b6ead74b5
soc: ll and hal for sleep related code
2020-08-17 19:09:24 +08:00
Armando
e58ce2141d
spi_master: rename the hal layer function that calculates clock and timing
2020-08-17 17:04:07 +08:00
Michael (XIAO Xufeng)
dc22501b47
Merge branch 'bugfix/mcpwm_capture_getedge_null_deref' into 'master'
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Bugfix(MCPWM): Fix dereferencing of a null pointer in function mcpwm_capture_signal_get_edge
See merge request espressif/esp-idf!9255
2020-08-17 15:52:24 +08:00
Angus Gratton
62c4b569ad
Merge branch 'refactor/timekeeping_init' into 'master'
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Timekeeping refactor
Closes IDF-1864
See merge request espressif/esp-idf!7824
2020-08-17 08:13:44 +08:00
morris
a3da67a97a
ethernet: set DMA owner after all descriptors have configured
2020-08-10 18:54:25 +08:00
morris
f4131b9b42
ethernet: handle early rx interrupt
2020-08-10 18:54:25 +08:00
morris
4e38aab1b0
ethernet: support flow control for esp32 emac
2020-08-10 18:54:25 +08:00
wubowen
de72ef2c1a
bugfix: Fixed the issue that calling mcpwm_capture_signal_get_edge causes a crash
2020-08-10 09:31:03 +00:00
Darian Leung
fdbda1ce78
TWAI: Simplify caps header
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This commit simplies the defines made in the _caps.h header. Kconfig
option dependencies were moved into the LL, and the check for a
valid BRP has bee simplified.
2020-08-10 17:01:32 +08:00
Darian Leung
d814a40c1d
TWAI: Fix ESP32-S2 register field name
2020-08-10 17:01:32 +08:00
Darian Leung
6983d1e0bb
TWAI: Fix BRP field initialization onf ESP32 ECO3
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This commit zero initializes the brp_div field on ESP32 ECO3
to prevent incorrect timing configuration.
2020-08-10 17:01:32 +08:00
Renz Bagaporo
5785e4dfb6
newlib: move some functions to soc, esp32, esp32s2
2020-08-10 15:11:38 +08:00
Michael (XIAO Xufeng)
cda9c595d7
Merge branch 'feature/mcpwm_capture_on_both_edge' into 'master'
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MCPWM: add an option to do mcpwm capture on both edges
See merge request espressif/esp-idf!9850
2020-08-10 11:48:50 +08:00
morris
edb5ddf63b
soc: placeholder for esp32s3 HAL driver
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soc rtc
2020-08-07 11:59:00 +08:00
Michael (XIAO Xufeng)
bfd71ae7ec
Merge branch 'feature/dma_memcpy' into 'master'
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esp32s2: async memcpy
Closes IDF-1573
See merge request espressif/esp-idf!8436
2020-08-06 11:32:43 +08:00
dongyou
97ae87df41
wifi, bt: move esp_phy_common_clock_disable into periph_ctrl and put it into IRAM
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Replace periph_module_enable/disable by periph_wifi_bt_common_module_enable which are in IRAM.
AddIRAM_ATTR periph_ll_wifi_bt_module_enable_clk_clear_rstandIRAM_ATTR periph_ll_wifi_bt_module_disable_clk_set_rstto fit O0 optimization level.
Delete duplicated spinlock and counter.
2020-08-05 11:04:16 +08:00
morris
b30bd7a2ef
esp32s2: add CP_DMA driver
2020-08-04 15:28:32 +08:00
Wu Bo Wen
14a6b1db56
driver/mcpwm: add an option to capture on both edges.
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However, The functionality of capturing on both edges is alternatively done with passing in the two flags ORed together: MCPWM_NEG_EDGE|MCPWM_POS_EDGE
closes https://github.com/espressif/esp-idf/issues/4446
closes https://github.com/espressif/esp-idf/issues/2943
2020-08-03 14:58:45 +08:00
Ivan Grokhotkov
0ee714e1fa
soc: move RTC initialization out of IRAM
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Saves approximately 870 bytes of IRAM.
2020-08-01 00:52:43 +02:00
Darian Leung
662864f5bc
twai: Fix size of RX msg count field on the esp32
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This commit fixes the size of the RX message count register field
on the esp32.
2020-07-30 15:45:58 +08:00
Angus Gratton
75402afcae
Merge branch 'feature/esp32s3_clk_memory_layout' into 'master'
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esp32s3: memory layout
See merge request espressif/esp-idf!9753
2020-07-29 13:48:25 +08:00
Michael (XIAO Xufeng)
6434c1e2bd
Merge branch 'feat/esp_flash_enable_s2_ut' into 'master'
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esp_flash: fix several issues and enable unit test for ESP32-S2
Closes IDF-1409
See merge request espressif/esp-idf!8259
2020-07-28 18:15:41 +08:00
Ivan Grokhotkov
16c73edc67
Merge branch 'refactor/add_alias_name_for_ets_common_api' into 'master'
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esp_rom: extract common ets apis into esp_rom_sys.h
See merge request espressif/esp-idf!9701
2020-07-28 15:04:55 +08:00
morris
2917651478
esp_rom: extract common ets apis into esp_rom_sys.h
2020-07-27 15:27:01 +08:00
morris
19761e3113
esp32s3: clk, memory layout
2020-07-27 13:05:22 +08:00
Michael (XIAO Xufeng)
30fa716376
spi: fix cs num support for different SPI hosts.
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For esp32, all SPI hosts have 3 CS pins, however, on ESP32, SPIMEM1 has
two CS pins, FSPI has six, while HSPI has three.
2020-07-27 12:27:03 +08:00
Michael (XIAO Xufeng)
4bad988317
esp_flash: fix slow read on ESP32-S2
2020-07-27 12:20:19 +08:00
fuzhibo
1568b6913d
driver(touch): fix touch sensor driver redundancy
2020-07-27 03:37:29 +00:00
Angus Gratton
442736c5d6
Merge branch 'refactor/common_rom_uart_apis' into 'master'
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esp_rom: extract common uart apis into esp_rom_uart.h
See merge request espressif/esp-idf!9313
2020-07-21 15:24:21 +08:00
Angus Gratton
3755fb6597
Merge branch 'feature/add_esp32s3_bootloader_ld_file' into 'master'
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move part of esp32-s3 codes to master (bootloader linker, esp32s3 empty componnet)
See merge request espressif/esp-idf!9608
2020-07-21 14:51:04 +08:00
chenjianqiang
e9dd4f283a
feat(esp32): support for esp32-pico-v3-02
2020-07-20 12:21:32 +08:00
morris
6316e6eba2
esp_system: add CONFIG_ESP_SYSTEM_RTC_EXT_CRYS
2020-07-20 11:15:24 +08:00
Angus Gratton
f83a61e2c8
Merge branch 'feature/ulp_riscv' into 'master'
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feature/components: Initial support for ULP-RISC-V Coprocessor on esp32s2
Closes IDF-521
See merge request espressif/esp-idf!8781
2020-07-20 08:27:20 +08:00
morris
345606e7f3
esp_rom: extract common uart apis into esp_rom_uart.h
2020-07-17 16:00:59 +08:00
Felipe Neves
b6dba84323
ulp: added support to building code for riscv ULP coprocessor
2020-07-15 15:28:49 -03:00
Michael (XIAO Xufeng)
c796bd5e63
esp_flash: refactor to make host driver function a const table
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This is also part of ESP32-S3 ROM changes
2020-07-13 03:10:00 +08:00
Michael (XIAO Xufeng)
a9c8895bb2
esp_flash: refactor to be compatible with the latest ROM
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Including:
1. Change the write bytes/read bytes parameter in the host driver into slicers to meet the requirements of complicated cases.
2. Refactor the esp_flash_api code a bit so that we can use the code in the ROM laster
3. Provide get_temp_buffer and release_temp_buffer in the os_functions when the buffer passed by application cannot be used directly.
4. Make timeout of operations configurable in the chip_driver.
5. Make dummy number configurable.
2020-07-12 02:09:45 +08:00
Michael (XIAO Xufeng)
f6dd63d03d
spi_slave_hd: new driver for spi slave in half duplex mode
2020-07-11 00:00:50 +08:00
Angus Gratton
fb192fd313
Merge branch 'bugfix/spinlock_coredump_regressions' into 'master'
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Bugfix/spinlock coredump regressions
Closes IDF-1901
See merge request espressif/esp-idf!9559
2020-07-10 14:01:08 +08:00
houwenxiang
166d5f17f3
driver(I2S): Fix I2S reset issue
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`i2s_start` reseting I2S in incorrect order causeing the word-order error.
closes https://github.com/espressif/esp-idf/issues/5410
2020-07-09 15:42:09 +00:00
Ivan Grokhotkov
4cdc5edb4e
Revert "freertos, soc: don't lower INTLEVEL when entering critical sections"
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This reverts commit 614a580bbb
.
2020-07-09 17:15:54 +02:00
morris
a4d0033c03
esp_rom: extract common GPIO apis into esp_rom_gpio.h
2020-07-07 11:40:19 +08:00
fuzhibo
8d922847af
driver(adc): esp32s2 support API adc2_vref_to_gpio
2020-07-01 06:21:45 +00:00
Darian Leung
97721d469c
TWAI: Add ESP32-S2 support
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This commit adds TWAI driver support for the
ESP32-S2. The following features were added:
- Expanded BRP support
- Expanded CLKOUT Divider Support
- Updated example READMEs
2020-06-30 16:56:03 +08:00
Ivan Grokhotkov
84833bf0df
Merge branch 'feature/light_sleep_reject' into 'master'
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sleep: enable sleep reject when entering light sleep
Closes IDF-1678 and WIFI-1185
See merge request espressif/esp-idf!9242
2020-06-29 15:57:49 +08:00
Ivan Grokhotkov
4e30e8801c
sleep: enable sleep reject when entering light sleep
2020-06-24 15:45:42 +00:00
Ivan Grokhotkov
0620890028
bootloader, rtc: don't disable PLL if it is already enabled
2020-06-24 15:50:51 +02:00
morris
4857dc5e2b
soc: add soc descriptions for esp32s3
2020-06-23 15:10:09 +08:00
Renz Bagaporo
08cbfa6187
esp_system: fix various review issues
2020-06-19 18:40:10 +10:00
Renz Christian Bagaporo
62ef63e835
esp32, esp32s2: move clk init functions to esp_system
2020-06-19 18:40:09 +10:00
Renz Bagaporo
39ef904fba
soc: introduce hal function for cpu delay
2020-06-19 18:40:09 +10:00
Ivan Grokhotkov
194353af07
soc: add periph_ll_periph_enabled to clk_gate_ll.h
2020-06-16 18:13:14 +02:00
Angus Gratton
61ab64439b
Merge branch 'bugfix/spi_flash_yield_coredump' into 'master'
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fixes for core dump regressions
See merge request espressif/esp-idf!8978
2020-06-16 12:15:50 +08:00
Angus Gratton
8193b188e8
driver: Fix some doxygen warnings
2020-06-12 14:31:37 +10:00
Ivan Grokhotkov
58e1100473
Merge branch 'bugfix/cast_int_to_size_t_in_cpu_ll' into 'master'
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soc: cast int to size_t in cpu_ll
Closes IDFGH-3352
See merge request espressif/esp-idf!9077
2020-06-08 15:40:42 +08:00
Michael (XIAO Xufeng)
1a6191debe
Merge branch 'bugfix/fix_ledc_unable_to_work_in_light_sleep_mode' into 'master'
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bugfix (Ledc): fix the bug that ledc low-speed channel can not work when chip in light-sleep mode
See merge request espressif/esp-idf!8392
2020-06-08 14:25:43 +08:00
Michael (XIAO Xufeng)
099f2706aa
Merge branch 'bugfix/fix_adc_dac_conflict' into 'master'
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Driver(adc): Disable the synchronization operation function of ADC1 and DAC
Closes IDF-1585
See merge request espressif/esp-idf!8364
2020-06-03 12:41:50 +08:00
Michael (XIAO Xufeng)
1a1b0574ac
Merge branch 'bugfix/fix_fifo_cnt_bug' into 'master'
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bugfix(uart): fix esp32 uart fifo_cnt bug
See merge request espressif/esp-idf!8974
2020-06-03 11:44:39 +08:00
Ivan Grokhotkov
614a580bbb
freertos, soc: don't lower INTLEVEL when entering critical sections
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This fixes the issue where XTOS_SET_INTLEVEL would lower INTLEVEL from
4 to 3, when eTaskGetState is invoked during the core dump, triggered
from the interrupt watchdog.
2020-06-02 15:42:24 +02:00
xiongyu
eea38d7698
bugfix(uart): fix esp32 fifo_cnt bug
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When using DPort to read fifo, fifo_cnt is not credible, we need to calculate the real cnt based on the fifo read and write pointer. When using AHB to read FIFO, we can use fifo_cnt to indicate the data length in fifo.
2020-06-02 21:38:31 +08:00
Michael (XIAO Xufeng)
d2bb1e1b75
Merge branch 'bugfix/fix_adc_dac_driver_ut' into 'master'
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Driver(adc): fix adc driver and UT
See merge request espressif/esp-idf!8482
2020-06-02 17:46:45 +08:00
fuzhibo
3cc2d0e9a4
Driver(adc): Disable the synchronization operation function of ADC1 and DAC
...
Closes IDF-1585
2020-06-01 16:23:47 +08:00
fuzhibo
d90e0e4345
driver(adc): fix unit test for ADC-DMA (test_esp32s2.c); fix unit test for ADC-DMA (test_esp32s2.c); fix commit in adc dirver.
2020-06-01 15:00:08 +08:00
houwenxiang
46713a5275
driver(uart): fix uart module reset issue
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On ESP32, due to fifo reset issue, UART2 will work incorrectly if reset the fifo of UART1(TX fifo and RX fifo). The software can workaround the RX fifo reset issue,
while the TX fifo reset issue can not. When UART2 is used and UART1 is used as the log output port, a software reset can reproduce this issue. So we should reset the UART memory
before the software reset to solve this problem.
2020-06-01 11:01:26 +08:00