Commit Graph

24 Commits

Author SHA1 Message Date
wanlei
15e8c04f7b spi: change linker file let spi hal able to out from iram 2023-04-21 18:58:36 +08:00
wuzhenghui
44df5b31af feature: add ram loadable app support 2023-02-01 17:57:22 +08:00
Cao Sen Miao
4713a9a7f2 ESP32H2: Introduce new chip target esp32h2, hello_world example supported 2022-12-29 12:29:14 +08:00
Song Ruo Jing
6a60ecf780 soc_caps: Introduce SOC_LEDC_SUPPORTED and SOC_I2C_SUPPORTED caps to IDF
Wrap the ledc, i2c source files with the new caps in CMakeLists and linker.lf.
This could avoid potential source file not found warning during linking time.
2022-08-31 20:43:22 +08:00
Fu Hanxi
0d7f5b3d84 adc: skip linking static functions when not COMPILER_OPTIMIZATION_DEFAULT 2022-08-29 16:57:31 +08:00
morris
cf4cfc69ed esp_adc: add test with -O0 2022-08-02 23:07:06 +08:00
Armando
5b523a3313 esp_adc: new esp_adc component and adc drivers 2022-07-15 18:31:00 +08:00
Darian Leung
a8a3756b38 hal: Route CPU and Interrupt Controller HAL/LL to esp_cpu calls
This commit makes changes to cpu_ll.h, cpu_hal.h, and interrupt_controller_hal.h:

- Moved to esp_hw_support in order to be deprecated in the future
- HAL/LL API now route their calls to esp_cpu.h functions instead

Also updated soc_hal.h as follows:

- Removed __SOC_HAL_..._OTHER_CORES() macros as they dependend on cpu_hal.h
- Made soc_hal.h and soc_ll.h interfaces always inline, and removed soc_hal.c.

This commit also updates the XCHAL_ERRATUM_572 workaround by

- Removing it's HAL function and invoking the workaround it directly the bootloader
- Added missing workaround for the ESP32-S3
2022-06-14 14:40:03 +08:00
morris
b2bb8fd3c4 rgb_lcd: support update pclk at runtime 2022-06-14 02:20:47 +00:00
morris
24f5fecef0 hal: use ROM implementation for systimer and wdt on esp32c2 2022-05-12 05:18:57 +00:00
wuzhenghui
961b08f1a7 hal: use WDT HAL IMPL in ESP32C2 ROM 2022-05-05 17:41:11 +08:00
wuzhenghui
17b3d139d5 hal: use systimer HAL IMPL in ESP32C2 ROM 2022-05-05 17:41:11 +08:00
songruojing
8d84033b8c gpio: Clean up unit tests and enable ci ut on some previously disabled test cases
Eliminate UT_T1_GPIO runner requirement by routing internally through gpio matrix and by setting gpio pins to GPIO_MODE_INPUT_OUTPUT mode for all interrupt related test cases.
2022-03-30 15:11:08 +08:00
Armando
c1cbd7bbf6 cache/mmu: implememnt cache and mmu hal APIs in bootloader 2022-03-11 22:43:11 +08:00
Ivan Grokhotkov
2ebde60cbb hal: fix CONFIG_TWAI_ISR_IN_IRAM not taking effect for C3/H2 2022-01-20 22:24:27 +01:00
laokaiyao
cf049e15ed esp8684: rename target to esp32c2 2022-01-19 11:08:57 +08:00
morris
5deb83b12d gptimer: new driver for previous timer group 2022-01-07 14:44:50 +08:00
Cao Sen Miao
09487761cf ESP8684: add freertos, hal, esp_system support 2021-11-06 17:33:44 +08:00
Shu Chen
205cd469e9 esp32h2: update driver/hal/soc components to support esp32h2 2021-07-01 19:53:11 +08:00
Cao Sen Miao
0d81edb174 spi_flash: refactoring flash encryption into new api 2021-04-25 17:09:25 +08:00
Omar Chebib
bb9aa806f7 panic: handlers can now be placed in flash
By unchecking "Place panic handler code in IRAM" in the menuconfig,
the panic handlers will be placed in flash. Of course, flash cache must
be activated when entering panic handlers.
2021-04-15 11:58:46 +08:00
Renz Bagaporo
d1c800fbbb components: fix ldgen check errors 2021-01-19 11:17:18 +08:00
Darian Leung
4c57f50fe4 TWAI: ISR runs when cache is disabled
This commit adds the feature where the TWAI ISR will continue to
run even if the cache is disabled. Whilst cache is disabled, any
received messages will go into the RX queue, and any pending TX
messages in the TX queue will be transmitted. This feature should
be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
2020-10-10 14:19:32 +08:00
Michael (XIAO Xufeng)
5425ef4ee4 hal: extract hal component from soc component 2020-09-01 13:25:32 +08:00