This commit fixes a bug where the portTRY_ENTER_CRITICAL_SAFE() for the
Xtensa and RISC-V FreeRTOS ports were broken as it did not correctly use
the timeout parameter.
Merges: https://github.com/espressif/esp-idf/pull/13022
- move .tbss to NOLOAD section
- remove xtensa-specific entities from riscv scripts
- explicit eh_frame terminator instead of "align magic"
- 80 characters line length limit
- refactor comments
- discard .rela sections (the rela data will go to relates sections)
fix(riscv): Updated RISC-V functions to set interrupt threshold for CLIC targets
Closes IDFCI-2033, IDFCI-2034, IDF-8090, and IDF-8117
See merge request espressif/esp-idf!29055
This commit introduce SOC_MEM_NON_CONTIGUOUS_SRAM flag (that enebled for
esp32p4). If SOC_MEM_NON_CONTIGUOUS_SRAM is enabled:
- LDFLAGS+=--enable-non-contiguous-regions
- ldgen.py replaces "arrays[*]" from sections.ld.in with objects under
SURROUND keyword. (e.g. from linker.lf: data -> dram0_data SURROUND(foo))
- "mapping[*]" - refers to all other data
If SOC_MEM_NON_CONTIGUOUS_SRAM, sections.ld.in file should contain at
least one block of code like this (otherwise it does not make sense):
.dram0.bss (NOLOAD) :
{
arrays[dram0_bss]
mapping[dram0_bss]
} > sram_low
.dram1.bss (NOLOAD) :
{
/* do not place here arrays[dram0_bss] because it may be splited
* between segments */
mapping[dram0_bss]
} > sram_high
This commit added the RISC-V utility functions to set the interrupt
threshold for CLIC targets by using direct register value writes.
This makes the functions more efficient during run-time.
This is done to improve the critical section enter and exit performance on esp32p4.
This commit does the following:
- removes the xCoreID member from the TCB when building for single-core
- xCoreID is no longer hard set to 0 when calling "PinnedToCore" task creation
functions in single-core
- Tidy up or add missing xCoreID asserts for functions that take xCoreID as an
argument:
- Functions that set/query a variable of a particular core will call
taskVALID_CORE_ID() to ensure ) 0 <= xCoreID < configNUMBER_OF_CORES
- Task creation functions that accept xCoreID also call taskVALID_CORE_ID()
but also allow tskNO_AFFINITY.
- Fix TaskStatus_t
- Remove xCoreID from TaskStatus_t if configTASKLIST_INCLUDE_COREID is not
defined.
- Set xCoreID to 0 when calling vTaskGetInfo() in single-core builds
This commit deprecates the "freertos/xtensa_context.h" and "xtensa/xtensa_context.h"
include paths. Users should use "xtensa_context.h" instead.
- Replace legacy include paths
- Removed some unnecessary includes of "xtensa_api.h"
- Add warning to compatibility header
This commit deprecates the "freertos/xtensa_api.h" and "xtensa/xtensa_api.h"
include paths. Users should use "xtensa_api.h" instead.
- Replace legacy include paths
- Removed some unnecessary includes of "xtensa_api.h"
- Replaced some calls with "esp_cpu_..." equivalents
- Add warning to compatibility header
This commit adds a taskVALID_CORE_ID() macro, similar to the one offered in
Amazon SMP FreeRTOS.
- Various functions have been updated to use that macro
- Removed some unecessary static asserts of CONFIG_FREERTOS_NO_AFFINITY and
added casting.
- Uncrustify changes
This commit mainly targets the ESP32-P4. It adds supports for coprocessors on
RISC-V based targets. The coprocessor save area, describing the used coprocessors
is stored at the end of the stack of each task (highest address) whereas each
coprocessor save area is allocated at the beginning of the task (lowest address).
The context of each coprocessor is saved lazily, by the task that want to use it.
Following the upgrade to FreeRTOS kernel v10.5.1, this commit updates the
version numbers, licenses, and SBOM files of FreeRTOS files to reflect v10.5.1.
Note:
- Updated licenses as v10.5.1 now uses SPDX format
- Removed CVE-2021-43997 as it was fixed post v10.4.5
This commit makes v10.5.1 the default FreeRTOS kernel in ESP-IDF by removing
the CONFIG_FREERTOS_USE_KERNEL_10_5_1 option and v10.4.3 specific code
blocks.
This commit fixes an issue where xPortCanYield() function may not be
able to detect an ISR context when HW interrupt nesting is active on
a CLIC interrupt controller such as on esp32p4.
This commit adds beta support for the FreeRTOS v10.5.1 kernel which can be
enabled by enabling the CONFIG_FREERTOS_USE_KERNEL_10_5_1 option.
The following changes have been made:
- Updated freertos/CMakeLists.txt to build v10.5.1 kernel with v10.4.3. ports
- Updated existing Xtensa and RISC-V ports to work with V10.5.1
- Modifications to other ESP-IDF components to work with v10.5.1
- Added some ESP-IDF specific tracing changes to v10.5.1 kernel
- Make CONFIG_FREERTOS_USE_KERNEL_10_5_1 a public option
Note: The beta release is missing some minor fixes, performance improvements,
and features. Using this beta release for production is not recommended.
Closes https://github.com/espressif/esp-idf/issues/7137
This commit updates the xPortCanYield() for esp32p4 by correcting the
return condition. Previously, the API would return true if an ISR of
priority 1 was received which is incorrect.
Previously, TLSP deletion callbacks were...
- Stored in a seprate TCB member "pvThreadLocalStoragePointersDelCallback"
- Called separately via multipole prvDeleteTLS() insertions in tasks.c
This commit refactors how TLSP deletion callbacks are stored and called:
- TLSP deletion callbacks are now stored in "pvThreadLocalStoragePointers"
directly. configNUM_THREAD_LOCAL_STORAGE_POINTERS is doubled in size so that
the deletion callbacks are stored in the latter half of the array
- The callbacks are now called via "portCLEAN_UP_TCB()". As such, the
prvDeleteTLS() additions are no longer needed and the function can be removed
- Removed some legacy TLSP tests using the old method of storing the callback
pointers.
This commit reduces the source code diff between IDF FreeRTOS and upstream
vanilla FreeRTOS, in preparation for v10.5.1 upgrade.
portCLEAN_UP_COPROC() was an IDF specific addition to FreeRTOS, where the
macro was called from prvDeleteTCB() to clean up the coprocessor context of a
deleted task.
This commit removes portCLEAN_UP_COPROC(). The coprocessor cleanup routine
(i.e., vPortCleanUpCoprocArea()) is now called via portCLEAN_UP_TCB()->
vPortTCBPreDeleteHook().
This removes a minor code difference between IDF FreeRTOS and upstream.
Previously, if CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP was enabled, users
would provide a definition for a vPortCleanUpTCB() hook function that is called
right before a task's memory is freed in prvDeleteTCB(). However,
vPortCleanUpTCB() will be reclaimed by ESP-IDF for internal use in v6.0.
This commit introduces the following changes...
Introduced a new CONFIG_FREERTOS_TASK_PRE_DELETION_HOOK option:
- Provides the same pre-deletion hook functionality. But users now define
vTaskPreDeletionHook() instead.
- CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP still exists, but is marked as
deprecated. This is to maintain compatibility with existing applications
that already define vPortCleanUpTCB().
- Removed redundant --wl --wrap workaround with vPortCleanUpTCB()
- Added todo notes to remove support for user defined vPortCleanUpTCB()
completely in v6.0.
- Updated test cases to use new CONFIG_FREERTOS_TASK_PRE_DELETION_HOOK option
Freed up portCLEAN_UP_TCB() to call a new internal vPortTCBPreDeleteHook():
- vPortTCBPreDeleteHook() now replaces the previous "wrapped" implementation
of vPortCleanUpTCB().
- vPortTCBPreDeleteHook() is an internal task pre-delete hook for IDF FreeRTOS
ports to inject some pre-deletion operations.
- Internal pre-delete hook now invokes user provided vTaskPreDeletionHook()
if enabled.
- Relocated vPortTCBPreDeleteHook() to correct section in port.c
portBASE_TYPE is an internal macro defined by the porting layer. This commit
changes all references to BaseType_t which is the official type exposed by
FreeRTOS.
portSTACK_TYPE is an internal macro defined by the porting layer. This commit
changes all references to StackType_t which is the official type exposed by
FreeRTOS.
- add hardware stack guard based on assist-debug module
- enable hardware stack guard by default
- disable hardware stack guard for freertos ci.release test
- refactor rtos_int_enter/rtos_int_exit to change SP register inside them
- fix panic_reason.h header for RISC-V
- update docs to include information about the new feature
* Added a POSIX/Linux simulator that is compatible with the Amazon
FreeRTOS SMP API. Note that the simulator itself is still
single core, like the IDF FreeRTOS POSIX/Linux simulator.
