alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

Merge branch 'fix/flash_freq_c5' into 'master'

Browse Source 
feat(spi_flash): Increase flash frequency from 40M to 80M

See merge request espressif/esp-idf!31967
This commit is contained in:
C.S.M 2024-07-11 17:41:04 +08:00
commit 5448703663
4 changed files with 44 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
components/esptool_py/Kconfig.projbuild
View File

@ -93,7 +93,7 @@ menu "Serial flasher config"
prompt "Flash SPI speed"
# TODO: [ESP32C5] IDF-8649 switch back to 80M
# TODO: [ESP32C61] IDF-9256
default ESPTOOLPY_FLASHFREQ_40M if IDF_TARGET_ESP32 || IDF_TARGET_ESP32C5 || IDF_TARGET_ESP32C61
default ESPTOOLPY_FLASHFREQ_40M if IDF_TARGET_ESP32 || IDF_TARGET_ESP32C61
default ESPTOOLPY_FLASHFREQ_80M if ESPTOOLPY_FLASHFREQ_80M_DEFAULT
default ESPTOOLPY_FLASHFREQ_60M if IDF_TARGET_ESP32C2
config ESPTOOLPY_FLASHFREQ_120M
@ -153,6 +153,7 @@ menu "Serial flasher config"
config ESPTOOLPY_FLASHFREQ_80M_DEFAULT
bool
default y if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C6
default y if IDF_TARGET_ESP32C5
help
This is an invisible item, used to define the targets that defaults to use 80MHz Flash SPI speed.

23
components/hal/esp32c5/include/hal/spimem_flash_ll.h
View File

@ -29,6 +29,8 @@
#include "hal/spi_flash_types.h"
#include "soc/pcr_struct.h"
#include "esp_rom_sys.h"
#include "hal/clk_tree_ll.h"
#include "soc/clk_tree_defs.h"
#ifdef __cplusplus
extern "C" {
@ -626,8 +628,25 @@ static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_
*/
static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void)
{
// TODO: [ESP32C5] IDF-8649
return 80;
int source_clk_mhz = 0;
switch (PCR.mspi_clk_conf.mspi_func_clk_sel)
{
case 0:
source_clk_mhz = clk_ll_xtal_get_freq_mhz();
break;
case 1:
source_clk_mhz = (SOC_CLK_RC_FAST_FREQ_APPROX/(1 * 1000 * 1000));
break;
case 2:
source_clk_mhz = clk_ll_bbpll_get_freq_mhz();
break;
default:
break;
}
uint8_t clock_val = source_clk_mhz / (PCR.mspi_clk_conf.mspi_fast_div_num + 1);
return clock_val;
}
/**

22
components/hal/esp32p4/include/hal/spimem_flash_ll.h
View File

@ -29,6 +29,7 @@
#include "hal/misc.h"
#include "hal/efuse_hal.h"
#include "soc/chip_revision.h"
#include "hal/clk_tree_ll.h"
#ifdef __cplusplus
extern "C" {
@ -645,7 +646,26 @@ static inline void spimem_flash_ll_set_extra_dummy(spi_mem_dev_t *dev, uint32_t
*/
static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void)
{
return 80;
// return 80;
int source_clk_mhz = 0;
switch (HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_clk_src_sel)
{
case 0:
source_clk_mhz = clk_ll_xtal_load_freq_mhz();
break;
case 1:
source_clk_mhz = CLK_LL_PLL_480M_FREQ_MHZ; // SPLL
break;
case 2:
source_clk_mhz = CLK_LL_PLL_400M_FREQ_MHZ; // CPLL
break;
default:
break;
}
uint8_t clock_val = source_clk_mhz / (HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_core_clk_div_num + 1);
return clock_val;
}
/**

1
components/soc/esp32c5/include/soc/soc_caps.h
View File

@ -424,7 +424,6 @@
// #define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
// #define SOC_SPI_MEM_SUPPORT_WRAP (1)
// TODO: [ESP32C5] IDF-8649
#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1